#include "cfi.h"
#include "non_cfi.h"
#include <target/arm.h>
+#include <target/arm7_9_common.h>
+#include <target/armv7m.h>
+#include <target/mips32.h>
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
/* defines internal maximum size for code fragment in cfi_intel_write_block() */
#define CFI_MAX_INTEL_CODESIZE 256
+/* some id-types with specific handling */
+#define AT49BV6416 0x00d6
+#define AT49BV6416T 0x00d2
+
static struct cfi_unlock_addresses cfi_unlock_addresses[] =
{
[CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
{CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
+ {CFI_MFR_SST, 0x274b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_SST, 0x236d, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
{CFI_MFR_ATMEL, 0x00C8, cfi_fixup_reversed_erase_regions, NULL},
{CFI_MFR_ST, 0x22C4, cfi_fixup_reversed_erase_regions, NULL}, /* M29W160ET */
{CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
{CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
+ {CFI_MFR_EON, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
{CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
{CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
{CFI_MFR_ST, 0x227E, cfi_fixup_0002_write_buffer, NULL}, /* M29W128G */
static void cfi_intel_clear_status_register(struct flash_bank *bank)
{
- struct target *target = bank->target;
-
- if (target->state != TARGET_HALTED)
- {
- LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
- exit(-1);
- }
-
cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
}
if (atmel_pri_ext.features & 0x02)
pri_ext->EraseSuspend = 2;
- if (atmel_pri_ext.bottom_boot)
- pri_ext->TopBottom = 2;
- else
- pri_ext->TopBottom = 3;
+ /* some chips got it backwards... */
+ if (cfi_info->device_id == AT49BV6416 ||
+ cfi_info->device_id == AT49BV6416T) {
+ if (atmel_pri_ext.bottom_boot)
+ pri_ext->TopBottom = 3;
+ else
+ pri_ext->TopBottom = 2;
+ } else {
+ if (atmel_pri_ext.bottom_boot)
+ pri_ext->TopBottom = 2;
+ else
+ pri_ext->TopBottom = 3;
+ }
pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
return cfi_intel_protect(bank, set, first, last);
break;
default:
- LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
- return ERROR_FAIL;
+ LOG_WARNING("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
+ return ERROR_OK;
}
}
* r6: error test pattern
*/
+ /* see contib/loaders/flash/armv4_5_cfi_intel_32.s for src */
static const uint32_t word_32_code[] = {
0xe4904004, /* loop: ldr r4, [r0], #4 */
0xe5813000, /* str r3, [r1] */
0xeafffffe /* done: b -2 */
};
+ /* see contib/loaders/flash/armv4_5_cfi_intel_16.s for src */
static const uint32_t word_16_code[] = {
0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
0xe1c130b0, /* strh r3, [r1] */
0xeafffffe /* done: b -2 */
};
+ /* see contib/loaders/flash/armv4_5_cfi_intel_8.s for src */
static const uint32_t word_8_code[] = {
0xe4d04001, /* loop: ldrb r4, [r0], #1 */
0xe5c13000, /* strb r3, [r1] */
uint32_t target_code_size;
int retval = ERROR_OK;
+ /* todo: if ( (!is_armv7m(target_to_armv7m(target)) && (!is_arm(target_to_arm(target)) ) */
+ if (strncmp(target_type_name(target),"mips_m4k",8) == 0)
+ {
+ LOG_ERROR("Your target has no flash block write support yet.");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
cfi_intel_clear_status_register(bank);
return retval;
}
+static int cfi_spansion_write_block_mips(struct flash_bank *bank, uint8_t *buffer,
+ uint32_t address, uint32_t count)
+{
+ struct cfi_flash_bank *cfi_info = bank->driver_priv;
+ struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
+ struct target *target = bank->target;
+ struct reg_param reg_params[10];
+ struct mips32_algorithm mips32_info;
+ struct working_area *source;
+ uint32_t buffer_size = 32768;
+ uint32_t status;
+ int retval = ERROR_OK;
+
+ /* input parameters - */
+ /* 4 A0 = source address */
+ /* 5 A1 = destination address */
+ /* 6 A2 = number of writes */
+ /* 7 A3 = flash write command */
+ /* 8 T0 = constant to mask DQ7 bits (also used for Dq5 with shift) */
+ /* output parameters - */
+ /* 9 T1 = 0x80 ok 0x00 bad */
+ /* temp registers - */
+ /* 10 T2 = value read from flash to test status */
+ /* 11 T3 = holding register */
+ /* unlock registers - */
+ /* 12 T4 = unlock1_addr */
+ /* 13 T5 = unlock1_cmd */
+ /* 14 T6 = unlock2_addr */
+ /* 15 T7 = unlock2_cmd */
+
+ static const uint32_t mips_word_16_code[] = {
+ /* start: */
+ MIPS32_LHU(9,0,4), /* lhu $t1, ($a0) ; out = &saddr */
+ MIPS32_ADDI(4,4,2), /* addi $a0, $a0, 2 ; saddr += 2 */
+ MIPS32_SH(13,0,12), /* sh $t5, ($t4) ; *fl_unl_addr1 = fl_unl_cmd1 */
+ MIPS32_SH(15,0,14), /* sh $t7, ($t6) ; *fl_unl_addr2 = fl_unl_cmd2 */
+ MIPS32_SH(7,0,12), /* sh $a3, ($t4) ; *fl_unl_addr1 = fl_write_cmd */
+ MIPS32_SH(9,0,5), /* sh $t1, ($a1) ; *daddr = out */
+ MIPS32_NOP, /* nop */
+ /* busy: */
+ MIPS32_LHU(10,0,5), /* lhu $t2, ($a1) ; temp1 = *daddr */
+ MIPS32_XOR(11,9,10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */
+ MIPS32_AND(11,8,11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */
+ MIPS32_BNE(11,8, 13), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */
+ MIPS32_NOP, /* nop */
+
+ MIPS32_SRL(10,8,2), /* srl $t2,$t0,2 ; temp1 = DQ7mask >> 2 */
+ MIPS32_AND(11,10,11), /* and $t3, $t2, $t3 ; temp2 = temp2 & temp1 */
+ MIPS32_BNE(11,10, NEG16(8)), /* bne $t3, $t2, busy ; if (temp2 != temp1) goto busy */
+ MIPS32_NOP, /* nop */
+
+ MIPS32_LHU(10,0,5), /* lhu $t2, ($a1) ; temp1 = *daddr */
+ MIPS32_XOR(11,9,10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */
+ MIPS32_AND(11,8,11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */
+ MIPS32_BNE(11,8, 4), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */
+ MIPS32_NOP, /* nop */
+
+ MIPS32_XOR(9,9,9), /* xor $t1, $t1, $t1 ; out = 0 */
+ MIPS32_BEQ(9,0, 11), /* beq $t1, $zero, done ; if (out == 0) goto done */
+ MIPS32_NOP, /* nop */
+ /* cont: */
+ MIPS32_ADDI(6,6,NEG16(1)), /* addi, $a2, $a2, -1 ; numwrites-- */
+ MIPS32_BNE(6,0, 5), /* bne $a2, $zero, cont2 ; if (numwrite != 0) goto cont2 */
+ MIPS32_NOP, /* nop */
+
+ MIPS32_LUI(9,0), /* lui $t1, 0 */
+ MIPS32_ORI(9,9,0x80), /* ori $t1, $t1, 0x80 ; out = 0x80 */
+
+ MIPS32_B(4), /* b done ; goto done */
+ MIPS32_NOP, /* nop */
+ /* cont2: */
+ MIPS32_ADDI(5,5,2), /* addi $a0, $a0, 2 ; daddr += 2 */
+ MIPS32_B(NEG16(33)), /* b start ; goto start */
+ MIPS32_NOP, /* nop */
+ /* done: */
+ /*MIPS32_B(NEG16(1)), */ /* b done ; goto done */
+ MIPS32_SDBBP, /* sdbbp ; break(); */
+ /*MIPS32_B(NEG16(33)), */ /* b start ; goto start */
+ /* MIPS32_NOP, */
+ };
+
+ mips32_info.common_magic = MIPS32_COMMON_MAGIC;
+ mips32_info.isa_mode = MIPS32_ISA_MIPS32;
+
+ int target_code_size = 0;
+ const uint32_t *target_code_src = NULL;
+
+ switch (bank->bus_width)
+ {
+ case 2 :
+ /* Check for DQ5 support */
+ if( cfi_info->status_poll_mask & (1 << 5) )
+ {
+ target_code_src = mips_word_16_code;
+ target_code_size = sizeof(mips_word_16_code);
+ }
+ else
+ {
+ LOG_ERROR("Need DQ5 support");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ //target_code_src = mips_word_16_code_dq7only;
+ //target_code_size = sizeof(mips_word_16_code_dq7only);
+ }
+ break;
+ default:
+ LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ /* flash write code */
+ if (!cfi_info->write_algorithm)
+ {
+ uint8_t *target_code;
+
+ /* convert bus-width dependent algorithm code to correct endiannes */
+ target_code = malloc(target_code_size);
+ if (target_code == NULL)
+ {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+ cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
+
+ /* allocate working area */
+ retval = target_alloc_working_area(target, target_code_size,
+ &cfi_info->write_algorithm);
+ if (retval != ERROR_OK)
+ {
+ free(target_code);
+ return retval;
+ }
+
+ /* write algorithm code to working area */
+ if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
+ target_code_size, target_code)) != ERROR_OK)
+ {
+ free(target_code);
+ return retval;
+ }
+
+ free(target_code);
+ }
+ /* the following code still assumes target code is fixed 24*4 bytes */
+
+ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
+ {
+ buffer_size /= 2;
+ if (buffer_size <= 256)
+ {
+ /* if we already allocated the writing code, but failed to get a
+ * buffer, free the algorithm */
+ if (cfi_info->write_algorithm)
+ target_free_working_area(target, cfi_info->write_algorithm);
+
+ LOG_WARNING("not enough working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ };
+
+ init_reg_param(®_params[0], "a0", 32, PARAM_OUT);
+ init_reg_param(®_params[1], "a1", 32, PARAM_OUT);
+ init_reg_param(®_params[2], "a2", 32, PARAM_OUT);
+ init_reg_param(®_params[3], "a3", 32, PARAM_OUT);
+ init_reg_param(®_params[4], "t0", 32, PARAM_OUT);
+ init_reg_param(®_params[5], "t1", 32, PARAM_IN);
+ init_reg_param(®_params[6], "t4", 32, PARAM_OUT);
+ init_reg_param(®_params[7], "t5", 32, PARAM_OUT);
+ init_reg_param(®_params[8], "t6", 32, PARAM_OUT);
+ init_reg_param(®_params[9], "t7", 32, PARAM_OUT);
+
+ while (count > 0)
+ {
+ uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
+
+ retval = target_write_buffer(target, source->address, thisrun_count, buffer);
+ if (retval != ERROR_OK)
+ {
+ break;
+ }
+
+ buf_set_u32(reg_params[0].value, 0, 32, source->address);
+ buf_set_u32(reg_params[1].value, 0, 32, address);
+ buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
+ buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
+ buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
+ buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
+ buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
+ buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
+ buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
+
+ retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
+ cfi_info->write_algorithm->address,
+ cfi_info->write_algorithm->address + ((target_code_size) - 4),
+ 10000, &mips32_info);
+ if (retval != ERROR_OK)
+ {
+ break;
+ }
+
+ status = buf_get_u32(reg_params[5].value, 0, 32);
+ if (status != 0x80)
+ {
+ LOG_ERROR("flash write block failed status: 0x%" PRIx32 , status);
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+
+ buffer += thisrun_count;
+ address += thisrun_count;
+ count -= thisrun_count;
+ }
+
+ target_free_all_working_areas(target);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+ destroy_reg_param(®_params[4]);
+ destroy_reg_param(®_params[5]);
+ destroy_reg_param(®_params[6]);
+ destroy_reg_param(®_params[7]);
+ destroy_reg_param(®_params[8]);
+ destroy_reg_param(®_params[9]);
+
+ return retval;
+}
+
static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
uint32_t address, uint32_t count)
{
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
- static const uint32_t word_32_code[] = {
+ /* see contib/loaders/flash/armv4_5_cfi_span_32.s for src */
+ static const uint32_t armv4_5_word_32_code[] = {
/* 00008100 <sp_32_code>: */
0xe4905004, /* ldr r5, [r0], #4 */
0xe5889000, /* str r9, [r8] */
/* */
/* 00008154 <sp_32_done>: */
0xeafffffe /* b 8154 <sp_32_done> */
- };
+ };
- static const uint32_t word_16_code[] = {
+ /* see contib/loaders/flash/armv4_5_cfi_span_16.s for src */
+ static const uint32_t armv4_5_word_16_code[] = {
/* 00008158 <sp_16_code>: */
0xe0d050b2, /* ldrh r5, [r0], #2 */
0xe1c890b0, /* strh r9, [r8] */
/* */
/* 000081ac <sp_16_done>: */
0xeafffffe /* b 81ac <sp_16_done> */
- };
+ };
+
+ /* see contib/loaders/flash/armv7m_cfi_span_16.s for src */
+ static const uint32_t armv7m_word_16_code[] = {
+ 0x5B02F830,
+ 0x9000F8A8,
+ 0xB000F8AA,
+ 0x3000F8A8,
+ 0xBF00800D,
+ 0xEA85880E,
+ 0x40270706,
+ 0xEA16D00A,
+ 0xD0F70694,
+ 0xEA85880E,
+ 0x40270706,
+ 0xF04FD002,
+ 0xD1070500,
+ 0xD0023A01,
+ 0x0102F101,
+ 0xF04FE7E0,
+ 0xE7FF0580,
+ 0x0000BE00
+ };
- static const uint32_t word_16_code_dq7only[] = {
+ /* see contib/loaders/flash/armv4_5_cfi_span_16_dq7.s for src */
+ static const uint32_t armv4_5_word_16_code_dq7only[] = {
/* <sp_16_code>: */
0xe0d050b2, /* ldrh r5, [r0], #2 */
0xe1c890b0, /* strh r9, [r8] */
/* */
/* 000081ac <sp_16_done>: */
0xeafffffe /* b 81ac <sp_16_done> */
- };
+ };
- static const uint32_t word_8_code[] = {
+ /* see contib/loaders/flash/armv4_5_cfi_span_8.s for src */
+ static const uint32_t armv4_5_word_8_code[] = {
/* 000081b0 <sp_16_code_end>: */
0xe4d05001, /* ldrb r5, [r0], #1 */
0xe5c89000, /* strb r9, [r8] */
0xeafffffe /* b 8204 <sp_8_done> */
};
- armv4_5_info.common_magic = ARM_COMMON_MAGIC;
- armv4_5_info.core_mode = ARM_MODE_SVC;
- armv4_5_info.core_state = ARM_STATE_ARM;
+ if (strncmp(target_type_name(target),"mips_m4k",8) == 0)
+ {
+ return cfi_spansion_write_block_mips(bank,buffer,address,count);
+ }
- int target_code_size;
- const uint32_t *target_code_src;
+ if (is_armv7m(target_to_armv7m(target))) /* Cortex-M3 target */
+ {
+ armv4_5_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv4_5_info.core_mode = ARMV7M_MODE_HANDLER;
+ armv4_5_info.core_state = ARM_STATE_ARM;
+ }
+ else
+ {
+ /* All other ARM CPUs have 32 bit instructions */
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
+ armv4_5_info.core_mode = ARM_MODE_SVC;
+ armv4_5_info.core_state = ARM_STATE_ARM;
+ }
+
+ int target_code_size = 0;
+ const uint32_t *target_code_src = NULL;
switch (bank->bus_width)
{
case 1 :
- target_code_src = word_8_code;
- target_code_size = sizeof(word_8_code);
+ if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) /* armv4_5 target */
+ {
+ target_code_src = armv4_5_word_8_code;
+ target_code_size = sizeof(armv4_5_word_8_code);
+ }
break;
case 2 :
/* Check for DQ5 support */
if( cfi_info->status_poll_mask & (1 << 5) )
{
- target_code_src = word_16_code;
- target_code_size = sizeof(word_16_code);
+ if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) /* armv4_5 target */
+ {
+ target_code_src = armv4_5_word_16_code;
+ target_code_size = sizeof(armv4_5_word_16_code);
+ }
+ else if (armv4_5_info.common_magic == ARMV7M_COMMON_MAGIC) /* cortex-m3 target */
+ {
+ target_code_src = armv7m_word_16_code;
+ target_code_size = sizeof(armv7m_word_16_code);
+ }
}
else
{
/* No DQ5 support. Use DQ7 DATA# polling only. */
- target_code_src = word_16_code_dq7only;
- target_code_size = sizeof(word_16_code_dq7only);
+ if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) // armv4_5 target
+ {
+ target_code_src = armv4_5_word_16_code_dq7only;
+ target_code_size = sizeof(armv4_5_word_16_code_dq7only);
+ }
}
break;
case 4 :
- target_code_src = word_32_code;
- target_code_size = sizeof(word_32_code);
+ if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) // armv4_5 target
+ {
+ target_code_src = armv4_5_word_32_code;
+ target_code_size = sizeof(armv4_5_word_32_code);
+ }
break;
default:
LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
- (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
- (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
- (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
- (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
-
- LOG_DEBUG("typ. word write timeout: %u us, typ. buf write timeout: %u us, "
- "typ. block erase timeout: %u ms, typ. chip erase timeout: %u ms",
- 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
- 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
-
- LOG_DEBUG("max. word write timeout: %u us, max. buf write timeout: %u us, "
- "max. block erase timeout: %u ms, max. chip erase timeout: %u ms",
- (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
- (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
- (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
- (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
-
- /* convert timeouts to real values in ms */
- cfi_info->word_write_timeout = DIV_ROUND_UP((1 << cfi_info->word_write_timeout_typ) *
- (1 << cfi_info->word_write_timeout_max), 1000);
- cfi_info->buf_write_timeout = DIV_ROUND_UP((1 << cfi_info->buf_write_timeout_typ) *
- (1 << cfi_info->buf_write_timeout_max), 1000);
- cfi_info->block_erase_timeout = (1 << cfi_info->block_erase_timeout_typ) *
- (1 << cfi_info->block_erase_timeout_max);
- cfi_info->chip_erase_timeout = (1 << cfi_info->chip_erase_timeout_typ) *
- (1 << cfi_info->chip_erase_timeout_max);
-
- LOG_DEBUG("calculated word write timeout: %u ms, buf write timeout: %u ms, "
- "block erase timeout: %u ms, chip erase timeout: %u ms",
- cfi_info->word_write_timeout, cfi_info->buf_write_timeout,
- cfi_info->block_erase_timeout, cfi_info->chip_erase_timeout);
-
uint8_t data;
retval = cfi_query_u8(bank, 0, 0x27, &data);
if (retval != ERROR_OK)
}
} /* end CFI case */
+ LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
+ (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
+ (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
+ (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
+ (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
+
+ LOG_DEBUG("typ. word write timeout: %u us, typ. buf write timeout: %u us, "
+ "typ. block erase timeout: %u ms, typ. chip erase timeout: %u ms",
+ 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
+ 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
+
+ LOG_DEBUG("max. word write timeout: %u us, max. buf write timeout: %u us, "
+ "max. block erase timeout: %u ms, max. chip erase timeout: %u ms",
+ (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
+ (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
+ (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
+ (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
+
+ /* convert timeouts to real values in ms */
+ cfi_info->word_write_timeout = DIV_ROUND_UP((1L << cfi_info->word_write_timeout_typ) *
+ (1L << cfi_info->word_write_timeout_max), 1000);
+ cfi_info->buf_write_timeout = DIV_ROUND_UP((1L << cfi_info->buf_write_timeout_typ) *
+ (1L << cfi_info->buf_write_timeout_max), 1000);
+ cfi_info->block_erase_timeout = (1L << cfi_info->block_erase_timeout_typ) *
+ (1L << cfi_info->block_erase_timeout_max);
+ cfi_info->chip_erase_timeout = (1L << cfi_info->chip_erase_timeout_typ) *
+ (1L << cfi_info->chip_erase_timeout_max);
+
+ LOG_DEBUG("calculated word write timeout: %u ms, buf write timeout: %u ms, "
+ "block erase timeout: %u ms, chip erase timeout: %u ms",
+ cfi_info->word_write_timeout, cfi_info->buf_write_timeout,
+ cfi_info->block_erase_timeout, cfi_info->chip_erase_timeout);
+
/* apply fixups depending on the primary command set */
switch (cfi_info->pri_id)
{
}
if (cfi_info->not_cfi == 0)
- printed = snprintf(buf, buf_size, "\ncfi information:\n");
+ printed = snprintf(buf, buf_size, "\nCFI flash: ");
else
- printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
+ printed = snprintf(buf, buf_size, "\nnon-CFI flash: ");
buf += printed;
buf_size -= printed;
- printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
+ printed = snprintf(buf, buf_size, "mfr: 0x%4.4x, id:0x%4.4x\n\n",
cfi_info->manufacturer, cfi_info->device_id);
buf += printed;
buf_size -= printed;
- if (cfi_info->not_cfi == 0)
- {
- printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: "
- "0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n",
- cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2],
- cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
- buf += printed;
- buf_size -= printed;
-
- printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, "
- "Vpp min: %u.%x, Vpp max: %u.%x\n",
- (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
- (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
- (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
- (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
- buf += printed;
- buf_size -= printed;
-
- printed = snprintf(buf, buf_size, "typ. word write timeout: %u us, "
- "typ. buf write timeout: %u us, "
- "typ. block erase timeout: %u ms, "
- "typ. chip erase timeout: %u ms\n",
- 1 << cfi_info->word_write_timeout_typ,
- 1 << cfi_info->buf_write_timeout_typ,
- 1 << cfi_info->block_erase_timeout_typ,
- 1 << cfi_info->chip_erase_timeout_typ);
- buf += printed;
- buf_size -= printed;
-
- printed = snprintf(buf, buf_size, "max. word write timeout: %u us, "
- "max. buf write timeout: %u us, max. "
- "block erase timeout: %u ms, max. chip erase timeout: %u ms\n",
- (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
- (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
- (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
- (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
- buf += printed;
- buf_size -= printed;
-
- printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, "
- "max buffer write size: 0x%x\n",
- cfi_info->dev_size,
- cfi_info->interface_desc,
- 1 << cfi_info->max_buf_write_size);
- buf += printed;
- buf_size -= printed;
+ printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: "
+ "0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n",
+ cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2],
+ cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
+ buf += printed;
+ buf_size -= printed;
- switch (cfi_info->pri_id)
- {
- case 1:
- case 3:
- cfi_intel_info(bank, buf, buf_size);
- break;
- case 2:
- cfi_spansion_info(bank, buf, buf_size);
- break;
- default:
- LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
- break;
- }
+ printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, "
+ "Vpp min: %u.%x, Vpp max: %u.%x\n",
+ (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
+ (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
+ (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
+ (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
+ buf += printed;
+ buf_size -= printed;
+
+ printed = snprintf(buf, buf_size, "typ. word write timeout: %u us, "
+ "typ. buf write timeout: %u us, "
+ "typ. block erase timeout: %u ms, "
+ "typ. chip erase timeout: %u ms\n",
+ 1 << cfi_info->word_write_timeout_typ,
+ 1 << cfi_info->buf_write_timeout_typ,
+ 1 << cfi_info->block_erase_timeout_typ,
+ 1 << cfi_info->chip_erase_timeout_typ);
+ buf += printed;
+ buf_size -= printed;
+
+ printed = snprintf(buf, buf_size, "max. word write timeout: %u us, "
+ "max. buf write timeout: %u us, max. "
+ "block erase timeout: %u ms, max. chip erase timeout: %u ms\n",
+ (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
+ (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
+ (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
+ (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
+ buf += printed;
+ buf_size -= printed;
+
+ printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, "
+ "max buffer write size: 0x%x\n",
+ cfi_info->dev_size,
+ cfi_info->interface_desc,
+ 1 << cfi_info->max_buf_write_size);
+ buf += printed;
+ buf_size -= printed;
+
+ switch (cfi_info->pri_id)
+ {
+ case 1:
+ case 3:
+ cfi_intel_info(bank, buf, buf_size);
+ break;
+ case 2:
+ cfi_spansion_info(bank, buf, buf_size);
+ break;
+ default:
+ LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
+ break;
}
return ERROR_OK;
projects / fw / openocd / blobdiff