cfi_info->pri_ext = NULL;
bank->driver_priv = cfi_info;
- cfi_info->write_algorithm = NULL;
-
cfi_info->x16_as_x8 = 0;
cfi_info->jedec_probe = 0;
cfi_info->not_cfi = 0;
cfi_info->jedec_probe = 1;
}
- cfi_info->write_algorithm = NULL;
-
/* bank wasn't probed yet */
cfi_info->qry[0] = 0xff;
static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
uint32_t address, uint32_t count)
{
- struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct target *target = bank->target;
struct reg_param reg_params[7];
struct arm_algorithm arm_algo;
+ struct working_area *write_algorithm;
struct working_area *source = NULL;
uint32_t buffer_size = 32768;
uint32_t write_command_val, busy_pattern_val, error_pattern_val;
uint32_t target_code_size;
int retval = ERROR_OK;
- /* todo: if ( (!is_armv7m(target_to_armv7m(target)) && (!is_arm(target_to_arm(target)) )
- **/
- if (strncmp(target_type_name(target), "mips_m4k", 8) == 0) {
- LOG_ERROR("Your target has no flash block write support yet.");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ /* check we have a supported arch */
+ if (is_arm(target_to_arm(target))) {
+ /* All other ARM CPUs have 32 bit instructions */
+ arm_algo.common_magic = ARM_COMMON_MAGIC;
+ arm_algo.core_mode = ARM_MODE_SVC;
+ arm_algo.core_state = ARM_STATE_ARM;
+ } else {
+ LOG_ERROR("Unknown architecture");
+ return ERROR_FAIL;
}
cfi_intel_clear_status_register(bank);
- arm_algo.common_magic = ARM_COMMON_MAGIC;
- arm_algo.core_mode = ARM_MODE_SVC;
- arm_algo.core_state = ARM_STATE_ARM;
-
/* If we are setting up the write_algorith, we need target_code_src
* if not we only need target_code_size. */
}
/* flash write code */
- if (!cfi_info->write_algorithm) {
- if (target_code_size > sizeof(target_code)) {
- LOG_WARNING("Internal error - target code buffer to small. "
+ if (target_code_size > sizeof(target_code)) {
+ LOG_WARNING("Internal error - target code buffer to small. "
"Increase CFI_MAX_INTEL_CODESIZE and recompile.");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
- cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
- /* Get memory for block write handler */
- retval = target_alloc_working_area(target,
- target_code_size,
- &cfi_info->write_algorithm);
- if (retval != ERROR_OK) {
- LOG_WARNING("No working area available, can't do block memory writes");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
- ;
+ /* Get memory for block write handler */
+ retval = target_alloc_working_area(target,
+ target_code_size,
+ &write_algorithm);
+ if (retval != ERROR_OK) {
+ LOG_WARNING("No working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ ;
- /* write algorithm code to working area */
- retval = target_write_buffer(target, cfi_info->write_algorithm->address,
- target_code_size, target_code);
- if (retval != ERROR_OK) {
- LOG_ERROR("Unable to write block write code to target");
- goto cleanup;
- }
+ /* write algorithm code to working area */
+ retval = target_write_buffer(target, write_algorithm->address,
+ target_code_size, target_code);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Unable to write block write code to target");
+ goto cleanup;
}
/* Get a workspace buffer for the data to flash starting with 32k size.
/* Execute algorithm, assume breakpoint for last instruction */
retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
- cfi_info->write_algorithm->address,
- cfi_info->write_algorithm->address + target_code_size -
+ write_algorithm->address,
+ write_algorithm->address + target_code_size -
sizeof(uint32_t),
10000, /* 10s should be enough for max. 32k of data */
&arm_algo);
if (source)
target_free_working_area(target, source);
- if (cfi_info->write_algorithm) {
- target_free_working_area(target, cfi_info->write_algorithm);
- cfi_info->write_algorithm = NULL;
- }
+ target_free_working_area(target, write_algorithm);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
struct target *target = bank->target;
struct reg_param reg_params[10];
struct mips32_algorithm mips32_info;
+ struct working_area *write_algorithm;
struct working_area *source;
uint32_t buffer_size = 32768;
uint32_t status;
}
/* flash write code */
- if (!cfi_info->write_algorithm) {
- uint8_t *target_code;
-
- /* convert bus-width dependent algorithm code to correct endiannes */
- target_code = malloc(target_code_size);
- if (target_code == NULL) {
- LOG_ERROR("Out of memory");
- return ERROR_FAIL;
- }
- cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
+ uint8_t *target_code;
- /* allocate working area */
- retval = target_alloc_working_area(target, target_code_size,
- &cfi_info->write_algorithm);
- if (retval != ERROR_OK) {
- free(target_code);
- return retval;
- }
+ /* convert bus-width dependent algorithm code to correct endiannes */
+ target_code = malloc(target_code_size);
+ if (target_code == NULL) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+ cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
- /* write algorithm code to working area */
- retval = target_write_buffer(target, cfi_info->write_algorithm->address,
- target_code_size, target_code);
- if (retval != ERROR_OK) {
- free(target_code);
- return retval;
- }
+ /* allocate working area */
+ retval = target_alloc_working_area(target, target_code_size,
+ &write_algorithm);
+ if (retval != ERROR_OK) {
+ free(target_code);
+ return retval;
+ }
+ /* write algorithm code to working area */
+ retval = target_write_buffer(target, write_algorithm->address,
+ target_code_size, target_code);
+ if (retval != ERROR_OK) {
free(target_code);
+ return retval;
}
+
+ free(target_code);
+
/* the following code still assumes target code is fixed 24*4 bytes */
while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
buffer_size /= 2;
if (buffer_size <= 256) {
- /* if we already allocated the writing code, but failed to get a
+ /* we already allocated the writing code, but failed to get a
* buffer, free the algorithm */
- if (cfi_info->write_algorithm)
- target_free_working_area(target, cfi_info->write_algorithm);
+ target_free_working_area(target, write_algorithm);
LOG_WARNING(
"not enough working area available, can't do block memory writes");
buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
- cfi_info->write_algorithm->address,
- cfi_info->write_algorithm->address + ((target_code_size) - 4),
+ write_algorithm->address,
+ write_algorithm->address + ((target_code_size) - 4),
10000, &mips32_info);
if (retval != ERROR_OK)
break;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
struct target *target = bank->target;
struct reg_param reg_params[10];
- struct arm_algorithm arm_algo;
+ void *arm_algo;
+ struct arm_algorithm armv4_5_algo;
+ struct armv7m_algorithm armv7m_algo;
+ struct working_area *write_algorithm;
struct working_area *source;
uint32_t buffer_size = 32768;
uint32_t status;
return cfi_spansion_write_block_mips(bank, buffer, address, count);
if (is_armv7m(target_to_armv7m(target))) { /* Cortex-M3 target */
- arm_algo.common_magic = ARMV7M_COMMON_MAGIC;
- arm_algo.core_mode = ARMV7M_MODE_HANDLER;
- arm_algo.core_state = ARM_STATE_ARM;
- } else if (is_arm7_9(target_to_arm7_9(target))) {
+ armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_algo.core_mode = ARMV7M_MODE_HANDLER;
+ arm_algo = &armv7m_algo;
+ } else if (is_arm(target_to_arm(target))) {
/* All other ARM CPUs have 32 bit instructions */
- arm_algo.common_magic = ARM_COMMON_MAGIC;
- arm_algo.core_mode = ARM_MODE_SVC;
- arm_algo.core_state = ARM_STATE_ARM;
+ armv4_5_algo.common_magic = ARM_COMMON_MAGIC;
+ armv4_5_algo.core_mode = ARM_MODE_SVC;
+ armv4_5_algo.core_state = ARM_STATE_ARM;
+ arm_algo = &armv4_5_algo;
} else {
LOG_ERROR("Unknown architecture");
return ERROR_FAIL;
switch (bank->bus_width) {
case 1:
- if (arm_algo.common_magic != ARM_COMMON_MAGIC) {
+ if (is_armv7m(target_to_armv7m(target))) {
LOG_ERROR("Unknown ARM architecture");
return ERROR_FAIL;
}
case 2:
/* Check for DQ5 support */
if (cfi_info->status_poll_mask & (1 << 5)) {
- if (arm_algo.common_magic == ARM_COMMON_MAGIC) {/* armv4_5 target */
- target_code_src = armv4_5_word_16_code;
- target_code_size = sizeof(armv4_5_word_16_code);
- } else if (arm_algo.common_magic == ARMV7M_COMMON_MAGIC) { /*
+ if (is_armv7m(target_to_armv7m(target))) { /*
*cortex-m3
*target
**/
target_code_src = armv7m_word_16_code;
target_code_size = sizeof(armv7m_word_16_code);
+ } else { /* armv4_5 target */
+ target_code_src = armv4_5_word_16_code;
+ target_code_size = sizeof(armv4_5_word_16_code);
}
} else {
/* No DQ5 support. Use DQ7 DATA# polling only. */
- if (arm_algo.common_magic != ARM_COMMON_MAGIC) {
+ if (is_armv7m(target_to_armv7m(target))) {
LOG_ERROR("Unknown ARM architecture");
return ERROR_FAIL;
}
}
break;
case 4:
- if (arm_algo.common_magic != ARM_COMMON_MAGIC) {
+ if (is_armv7m(target_to_armv7m(target))) {
LOG_ERROR("Unknown ARM architecture");
return ERROR_FAIL;
}
}
/* flash write code */
- if (!cfi_info->write_algorithm) {
- uint8_t *target_code;
+ uint8_t *target_code;
- /* convert bus-width dependent algorithm code to correct endiannes */
- target_code = malloc(target_code_size);
- if (target_code == NULL) {
- LOG_ERROR("Out of memory");
- return ERROR_FAIL;
- }
- cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
-
- /* allocate working area */
- retval = target_alloc_working_area(target, target_code_size,
- &cfi_info->write_algorithm);
- if (retval != ERROR_OK) {
- free(target_code);
- return retval;
- }
+ /* convert bus-width dependent algorithm code to correct endiannes */
+ target_code = malloc(target_code_size);
+ if (target_code == NULL) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+ cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
- /* write algorithm code to working area */
- retval = target_write_buffer(target, cfi_info->write_algorithm->address,
- target_code_size, target_code);
- if (retval != ERROR_OK) {
- free(target_code);
- return retval;
- }
+ /* allocate working area */
+ retval = target_alloc_working_area(target, target_code_size,
+ &write_algorithm);
+ if (retval != ERROR_OK) {
+ free(target_code);
+ return retval;
+ }
+ /* write algorithm code to working area */
+ retval = target_write_buffer(target, write_algorithm->address,
+ target_code_size, target_code);
+ if (retval != ERROR_OK) {
free(target_code);
+ return retval;
}
+
+ free(target_code);
+
/* the following code still assumes target code is fixed 24*4 bytes */
while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
buffer_size /= 2;
if (buffer_size <= 256) {
- /* if we already allocated the writing code, but failed to get a
+ /* we already allocated the writing code, but failed to get a
* buffer, free the algorithm */
- if (cfi_info->write_algorithm)
- target_free_working_area(target, cfi_info->write_algorithm);
+ target_free_working_area(target, write_algorithm);
LOG_WARNING(
"not enough working area available, can't do block memory writes");
buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
- cfi_info->write_algorithm->address,
- cfi_info->write_algorithm->address + ((target_code_size) - 4),
- 10000, &arm_algo);
+ write_algorithm->address,
+ write_algorithm->address + ((target_code_size) - 4),
+ 10000, arm_algo);
if (retval != ERROR_OK)
break;
projects / fw / openocd / blobdiff