struct target *target = bank->target;
uint32_t buffer_size = 16384 + 8;
struct working_area *write_algorithm;
- struct working_area *write_algorithm_sp;
+ struct working_area *write_algorithm_stack;
struct working_area *source;
uint32_t address = bank->base + offset;
struct reg_param reg_params[5];
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
- /* Stack pointer area */
+ /* Stack area */
if (target_alloc_working_area(target, 128,
- &write_algorithm_sp) != ERROR_OK) {
- LOG_DEBUG("no working area for write code stack pointer");
+ &write_algorithm_stack) != ERROR_OK) {
+ LOG_DEBUG("no working area for target algorithm stack");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
init_reg_param(®_params[4], "sp", 32, PARAM_OUT);
- /* Put the parameter at the first available stack location */
- init_mem_param(&mem_params[0], write_algorithm_sp->address + 80, 32, PARAM_OUT);
+ /* Put the 4th parameter at the location in the stack frame of target write() function.
+ * See contrib/loaders/flash/bluenrg-x/bluenrg-x_write.lst
+ * 34 ldr r6, [sp, #80]
+ * ^^^ offset
+ */
+ init_mem_param(&mem_params[0], write_algorithm_stack->address + 80, 32, PARAM_OUT);
+ /* Stack for target write algorithm - target write() function has
+ * __attribute__((naked)) so it does not setup the new stack frame.
+ * Therefore the stack frame uses the area from SP upwards!
+ * Interrupts are disabled and no subroutines are called from write()
+ * so no need to allocate stack below SP.
+ * TODO: remove __attribute__((naked)) and use similar parameter passing as stm32l4x */
+ buf_set_u32(reg_params[4].value, 0, 32, write_algorithm_stack->address);
/* FIFO start address (first two words used for write and read pointers) */
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[2].value, 0, 32, address);
/* Number of bytes */
buf_set_u32(reg_params[3].value, 0, 32, count);
- /* Stack pointer for program working area */
- buf_set_u32(reg_params[4].value, 0, 32, write_algorithm_sp->address);
/* Flash register base address */
buf_set_u32(mem_params[0].value, 0, 32, bluenrgx_info->flash_ptr->flash_regs_base);
LOG_DEBUG("source->address = " TARGET_ADDR_FMT, source->address);
LOG_DEBUG("source->address+ source->size = " TARGET_ADDR_FMT, source->address+source->size);
- LOG_DEBUG("write_algorithm_sp->address = " TARGET_ADDR_FMT, write_algorithm_sp->address);
+ LOG_DEBUG("write_algorithm_stack->address = " TARGET_ADDR_FMT, write_algorithm_stack->address);
LOG_DEBUG("address = %08" PRIx32, address);
LOG_DEBUG("count = %08" PRIx32, count);
}
target_free_working_area(target, source);
target_free_working_area(target, write_algorithm);
- target_free_working_area(target, write_algorithm_sp);
+ target_free_working_area(target, write_algorithm_stack);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);