Add support for the ATMEL SAM G55 Xplained Pro board and CPU.

[fw/openocd] / src / flash / nor / at91sam4.c

diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index 94d5bfda4e663e0b24259b92163fd224d2ae5733..ff75b4188325dc06160a9e976a04ee13bc73114f 100644 (file)
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -1340,6 +1340,74 @@ static const struct sam4_chip_details all_sam4_details[] = {
                }
        },
 
+       /* atsamg55g19 */
+       {
+               .chipid_cidr    = 0x24470ae0,
+               .name           = "atsamg55g19",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 160 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+
+               {
+/*                     .bank[0] = */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 5,
+                               .present = 1,
+                               .size_bytes =  512 * 1024,
+                               .nsectors   =  64,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+/*                     .bank[1] = */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
+               }
+       },
+
+       /* atsamg55j19 */
+       {
+               .chipid_cidr    = 0x24570ae0,
+               .name           = "atsamg55j19",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 160 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+
+               {
+/*                     .bank[0] = */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 5,
+                               .present = 1,
+                               .size_bytes =  512 * 1024,
+                               .nsectors   =  64,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+/*                     .bank[1] = */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
+               }
+       },
+
        /* terminate */
        {
                .chipid_cidr    = 0,
@@ -1917,6 +1985,8 @@ static const struct archnames { unsigned value; const char *name; } archnames[]
        { 0x42,  "AT91x42 Series"                                                       },
        { 0x43,  "SAMG51 Series"
        },
+       { 0x44,  "SAMG55 Series (49-pin WLCSP)"                                         },
+       { 0x45,  "SAMG55 Series (64-pin)"                                                        },
        { 0x47,  "SAMG53 Series"
        },
        { 0x55,  "AT91x55 Series"                                                       },