* Copyright (C) 2009 by Duane Ellis *
* openocd@duaneellis.com *
* *
+ * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
+ * olaf@uni-paderborn.de *
+ * *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
#include "imp.h"
-#include "at91sam3.h"
-#include <helper/membuf.h>
#include <helper/time_support.h>
#define REG_NAME_WIDTH (12)
+// at91sam3u series (has one or two flash banks)
+#define FLASH_BANK0_BASE_U 0x00080000
+#define FLASH_BANK1_BASE_U 0x00100000
-#define FLASH_BANK0_BASE 0x00080000
-#define FLASH_BANK1_BASE 0x00100000
+// at91sam3s series (has always one flash bank)
+#define FLASH_BANK_BASE_S 0x00400000
+
+// at91sam3n series (has always one flash bank)
+#define FLASH_BANK_BASE_N 0x00400000
#define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
#define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
#define offset_EFC_FRR 12
+extern struct flash_driver at91sam3_flash;
+
static float
_tomhz(uint32_t freq_hz)
{
uint32_t PMC_FSPR;
};
+/*
+ * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
+ * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
+ * the flash wait state (FWS) should be set to 6. It seems like that the
+ * cause of the problem is not the flash itself, but the flash write
+ * buffer. Ie the wait states have to be set before writing into the
+ * buffer.
+ * Tested and confirmed with SAM3N and SAM3U
+ */
struct sam3_bank_private {
int probed;
unsigned bank_number;
uint32_t controller_address;
uint32_t base_address;
+ uint32_t flash_wait_states;
bool present;
unsigned size_bytes;
unsigned nsectors;
struct sam3_chip_details details;
struct target *target;
struct sam3_cfg cfg;
-
- struct membuf *mbuf;
};
}
-// these are used to *initialize* the "pChip->details" structure.
-static const struct sam3_chip_details all_sam3_details[] = {
+// these are used to *initialize* the "pChip->details" structure.
+static const struct sam3_chip_details all_sam3_details[] = {
+ // Start at91sam3u* series
+ {
+ .chipid_cidr = 0x28100960,
+ .name = "at91sam3u4e",
+ .total_flash_size = 256 * 1024,
+ .total_sram_size = 52 * 1024,
+ .n_gpnvms = 3,
+ .n_banks = 2,
+
+ // System boots at address 0x0
+ // gpnvm[1] = selects boot code
+ // if gpnvm[1] == 0
+ // boot is via "SAMBA" (rom)
+ // else
+ // boot is via FLASH
+ // Selection is via gpnvm[2]
+ // endif
+ //
+ // NOTE: banks 0 & 1 switch places
+ // if gpnvm[2] == 0
+ // Bank0 is the boot rom
+ // else
+ // Bank1 is the boot rom
+ // endif
+// .bank[0] = {
+ {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK0_BASE_U,
+ .controller_address = 0x400e0800,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 128 * 1024,
+ .nsectors = 16,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+
+// .bank[1] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 1,
+ .base_address = FLASH_BANK1_BASE_U,
+ .controller_address = 0x400e0a00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 128 * 1024,
+ .nsectors = 16,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+ },
+ },
+
+ {
+ .chipid_cidr = 0x281a0760,
+ .name = "at91sam3u2e",
+ .total_flash_size = 128 * 1024,
+ .total_sram_size = 36 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+
+ // System boots at address 0x0
+ // gpnvm[1] = selects boot code
+ // if gpnvm[1] == 0
+ // boot is via "SAMBA" (rom)
+ // else
+ // boot is via FLASH
+ // Selection is via gpnvm[2]
+ // endif
+// .bank[0] = {
+ {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK0_BASE_U,
+ .controller_address = 0x400e0800,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 128 * 1024,
+ .nsectors = 16,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x28190560,
+ .name = "at91sam3u1e",
+ .total_flash_size = 64 * 1024,
+ .total_sram_size = 20 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+
+ // System boots at address 0x0
+ // gpnvm[1] = selects boot code
+ // if gpnvm[1] == 0
+ // boot is via "SAMBA" (rom)
+ // else
+ // boot is via FLASH
+ // Selection is via gpnvm[2]
+ // endif
+ //
+
+// .bank[0] = {
+ {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK0_BASE_U,
+ .controller_address = 0x400e0800,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 64 * 1024,
+ .nsectors = 8,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+ },
+ },
+ },
+
+ {
+ .chipid_cidr = 0x28000960,
+ .name = "at91sam3u4c",
+ .total_flash_size = 256 * 1024,
+ .total_sram_size = 52 * 1024,
+ .n_gpnvms = 3,
+ .n_banks = 2,
+
+ // System boots at address 0x0
+ // gpnvm[1] = selects boot code
+ // if gpnvm[1] == 0
+ // boot is via "SAMBA" (rom)
+ // else
+ // boot is via FLASH
+ // Selection is via gpnvm[2]
+ // endif
+ //
+ // NOTE: banks 0 & 1 switch places
+ // if gpnvm[2] == 0
+ // Bank0 is the boot rom
+ // else
+ // Bank1 is the boot rom
+ // endif
+ {
+ {
+// .bank[0] = {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK0_BASE_U,
+ .controller_address = 0x400e0800,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 128 * 1024,
+ .nsectors = 16,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 1,
+ .base_address = FLASH_BANK1_BASE_U,
+ .controller_address = 0x400e0a00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 128 * 1024,
+ .nsectors = 16,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+ },
+ },
+
+ {
+ .chipid_cidr = 0x280a0760,
+ .name = "at91sam3u2c",
+ .total_flash_size = 128 * 1024,
+ .total_sram_size = 36 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+
+ // System boots at address 0x0
+ // gpnvm[1] = selects boot code
+ // if gpnvm[1] == 0
+ // boot is via "SAMBA" (rom)
+ // else
+ // boot is via FLASH
+ // Selection is via gpnvm[2]
+ // endif
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK0_BASE_U,
+ .controller_address = 0x400e0800,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 128 * 1024,
+ .nsectors = 16,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x28090560,
+ .name = "at91sam3u1c",
+ .total_flash_size = 64 * 1024,
+ .total_sram_size = 20 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+
+ // System boots at address 0x0
+ // gpnvm[1] = selects boot code
+ // if gpnvm[1] == 0
+ // boot is via "SAMBA" (rom)
+ // else
+ // boot is via FLASH
+ // Selection is via gpnvm[2]
+ // endif
+ //
+
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK0_BASE_U,
+ .controller_address = 0x400e0800,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 64 * 1024,
+ .nsectors = 8,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+
+ // Start at91sam3s* series
+
+ // Note: The preliminary at91sam3s datasheet says on page 302
+ // that the flash controller is at address 0x400E0800.
+ // This is _not_ the case, the controller resides at address 0x400e0a0.
+ {
+ .chipid_cidr = 0x28A00960,
+ .name = "at91sam3s4c",
+ .total_flash_size = 256 * 1024,
+ .total_sram_size = 48 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+ .controller_address = 0x400e0a00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 256 * 1024,
+ .nsectors = 32,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+
+ {
+ .chipid_cidr = 0x28900960,
+ .name = "at91sam3s4b",
+ .total_flash_size = 256 * 1024,
+ .total_sram_size = 48 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+ .controller_address = 0x400e0a00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 256 * 1024,
+ .nsectors = 32,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x28800960,
+ .name = "at91sam3s4a",
+ .total_flash_size = 256 * 1024,
+ .total_sram_size = 48 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+ .controller_address = 0x400e0a00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 256 * 1024,
+ .nsectors = 32,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x28AA0760,
+ .name = "at91sam3s2c",
+ .total_flash_size = 128 * 1024,
+ .total_sram_size = 32 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+ .controller_address = 0x400e0a00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 128 * 1024,
+ .nsectors = 16,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x289A0760,
+ .name = "at91sam3s2b",
+ .total_flash_size = 128 * 1024,
+ .total_sram_size = 32 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+ .controller_address = 0x400e0a00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 128 * 1024,
+ .nsectors = 16,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x288A0760,
+ .name = "at91sam3s2a",
+ .total_flash_size = 128 * 1024,
+ .total_sram_size = 32 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+ .controller_address = 0x400e0a00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 128 * 1024,
+ .nsectors = 16,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x28A90560,
+ .name = "at91sam3s1c",
+ .total_flash_size = 64 * 1024,
+ .total_sram_size = 16 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+ .controller_address = 0x400e0a00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 64 * 1024,
+ .nsectors = 8,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x28990560,
+ .name = "at91sam3s1b",
+ .total_flash_size = 64 * 1024,
+ .total_sram_size = 16 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+ .controller_address = 0x400e0a00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 64 * 1024,
+ .nsectors = 8,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x28890560,
+ .name = "at91sam3s1a",
+ .total_flash_size = 64 * 1024,
+ .total_sram_size = 16 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+ .controller_address = 0x400e0a00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 64 * 1024,
+ .nsectors = 8,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+
+ // Start at91sam3n* series
+ {
+ .chipid_cidr = 0x29540960,
+ .name = "at91sam3n4c",
+ .total_flash_size = 256 * 1024,
+ .total_sram_size = 24 * 1024,
+ .n_gpnvms = 3,
+ .n_banks = 1,
+
+ // System boots at address 0x0
+ // gpnvm[1] = selects boot code
+ // if gpnvm[1] == 0
+ // boot is via "SAMBA" (rom)
+ // else
+ // boot is via FLASH
+ // Selection is via gpnvm[2]
+ // endif
+ //
+ // NOTE: banks 0 & 1 switch places
+ // if gpnvm[2] == 0
+ // Bank0 is the boot rom
+ // else
+ // Bank1 is the boot rom
+ // endif
+// .bank[0] = {
+ {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_N,
+ .controller_address = 0x400e0A00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 256 * 1024,
+ .nsectors = 16,
+ .sector_size = 16384,
+ .page_size = 256,
+ },
+
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+ },
+ },
+ },
+
{
- .chipid_cidr = 0x28100960,
- .name = "at91sam3u4e",
+ .chipid_cidr = 0x29440960,
+ .name = "at91sam3n4b",
.total_flash_size = 256 * 1024,
- .total_sram_size = 52 * 1024,
+ .total_sram_size = 24 * 1024,
.n_gpnvms = 3,
- .n_banks = 2,
+ .n_banks = 1,
// System boots at address 0x0
// gpnvm[1] = selects boot code
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
- .base_address = FLASH_BANK0_BASE,
- .controller_address = 0x400e0800,
+ .base_address = FLASH_BANK_BASE_N,
+ .controller_address = 0x400e0A00,
+ .flash_wait_states = 6, /* workaround silicon bug */
.present = 1,
- .size_bytes = 128 * 1024,
+ .size_bytes = 256 * 1024,
.nsectors = 16,
- .sector_size = 8192,
+ .sector_size = 16384,
.page_size = 256,
},
// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+ },
+ },
+ },
+
+ {
+ .chipid_cidr = 0x29340960,
+ .name = "at91sam3n4a",
+ .total_flash_size = 256 * 1024,
+ .total_sram_size = 24 * 1024,
+ .n_gpnvms = 3,
+ .n_banks = 1,
+
+ // System boots at address 0x0
+ // gpnvm[1] = selects boot code
+ // if gpnvm[1] == 0
+ // boot is via "SAMBA" (rom)
+ // else
+ // boot is via FLASH
+ // Selection is via gpnvm[2]
+ // endif
+ //
+ // NOTE: banks 0 & 1 switch places
+ // if gpnvm[2] == 0
+ // Bank0 is the boot rom
+ // else
+ // Bank1 is the boot rom
+ // endif
+// .bank[0] = {
+ {
{
.probed = 0,
.pChip = NULL,
.pBank = NULL,
- .bank_number = 1,
- .base_address = FLASH_BANK1_BASE,
- .controller_address = 0x400e0a00,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_N,
+ .controller_address = 0x400e0A00,
+ .flash_wait_states = 6, /* workaround silicon bug */
.present = 1,
- .size_bytes = 128 * 1024,
+ .size_bytes = 256 * 1024,
.nsectors = 16,
- .sector_size = 8192,
+ .sector_size = 16384,
.page_size = 256,
},
+
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+ },
},
},
{
- .chipid_cidr = 0x281a0760,
- .name = "at91sam3u2e",
+ .chipid_cidr = 0x29590760,
+ .name = "at91sam3n2c",
.total_flash_size = 128 * 1024,
- .total_sram_size = 36 * 1024,
- .n_gpnvms = 2,
+ .total_sram_size = 16 * 1024,
+ .n_gpnvms = 3,
.n_banks = 1,
// System boots at address 0x0
// boot is via FLASH
// Selection is via gpnvm[2]
// endif
+ //
+ // NOTE: banks 0 & 1 switch places
+ // if gpnvm[2] == 0
+ // Bank0 is the boot rom
+ // else
+ // Bank1 is the boot rom
+ // endif
// .bank[0] = {
{
{
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
- .base_address = FLASH_BANK0_BASE,
- .controller_address = 0x400e0800,
+ .base_address = FLASH_BANK_BASE_N,
+ .controller_address = 0x400e0A00,
+ .flash_wait_states = 6, /* workaround silicon bug */
.present = 1,
.size_bytes = 128 * 1024,
- .nsectors = 16,
- .sector_size = 8192,
+ .nsectors = 8,
+ .sector_size = 16384,
.page_size = 256,
},
-// .bank[1] = {
+
+// .bank[1] = {
{
- .present = 0,
+ .present = 0,
.probed = 0,
.bank_number = 1,
},
},
},
+
{
- .chipid_cidr = 0x28190560,
- .name = "at91sam3u1e",
- .total_flash_size = 64 * 1024,
- .total_sram_size = 20 * 1024,
- .n_gpnvms = 2,
+ .chipid_cidr = 0x29490760,
+ .name = "at91sam3n2b",
+ .total_flash_size = 128 * 1024,
+ .total_sram_size = 16 * 1024,
+ .n_gpnvms = 3,
.n_banks = 1,
// System boots at address 0x0
// Selection is via gpnvm[2]
// endif
//
-
+ // NOTE: banks 0 & 1 switch places
+ // if gpnvm[2] == 0
+ // Bank0 is the boot rom
+ // else
+ // Bank1 is the boot rom
+ // endif
// .bank[0] = {
{
{
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
- .base_address = FLASH_BANK0_BASE,
- .controller_address = 0x400e0800,
+ .base_address = FLASH_BANK_BASE_N,
+ .controller_address = 0x400e0A00,
+ .flash_wait_states = 6, /* workaround silicon bug */
.present = 1,
- .size_bytes = 64 * 1024,
- .nsectors = 8,
- .sector_size = 8192,
+ .size_bytes = 128 * 1024,
+ .nsectors = 8,
+ .sector_size = 16384,
.page_size = 256,
},
// .bank[1] = {
{
- .present = 0,
+ .present = 0,
.probed = 0,
.bank_number = 1,
},
},
{
- .chipid_cidr = 0x28000960,
- .name = "at91sam3u4c",
- .total_flash_size = 256 * 1024,
- .total_sram_size = 52 * 1024,
+ .chipid_cidr = 0x29390760,
+ .name = "at91sam3n2a",
+ .total_flash_size = 128 * 1024,
+ .total_sram_size = 16 * 1024,
.n_gpnvms = 3,
- .n_banks = 2,
+ .n_banks = 1,
// System boots at address 0x0
// gpnvm[1] = selects boot code
// else
// Bank1 is the boot rom
// endif
+// .bank[0] = {
{
{
-// .bank[0] = {
.probed = 0,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
- .base_address = FLASH_BANK0_BASE,
- .controller_address = 0x400e0800,
+ .base_address = FLASH_BANK_BASE_N,
+ .controller_address = 0x400e0A00,
+ .flash_wait_states = 6, /* workaround silicon bug */
.present = 1,
.size_bytes = 128 * 1024,
- .nsectors = 16,
- .sector_size = 8192,
+ .nsectors = 8,
+ .sector_size = 16384,
.page_size = 256,
},
+
// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+ },
+ },
+ },
+
+ {
+ .chipid_cidr = 0x29580560,
+ .name = "at91sam3n1c",
+ .total_flash_size = 64 * 1024,
+ .total_sram_size = 8 * 1024,
+ .n_gpnvms = 3,
+ .n_banks = 1,
+
+ // System boots at address 0x0
+ // gpnvm[1] = selects boot code
+ // if gpnvm[1] == 0
+ // boot is via "SAMBA" (rom)
+ // else
+ // boot is via FLASH
+ // Selection is via gpnvm[2]
+ // endif
+ //
+ // NOTE: banks 0 & 1 switch places
+ // if gpnvm[2] == 0
+ // Bank0 is the boot rom
+ // else
+ // Bank1 is the boot rom
+ // endif
+// .bank[0] = {
+ {
{
.probed = 0,
.pChip = NULL,
.pBank = NULL,
- .bank_number = 1,
- .base_address = FLASH_BANK1_BASE,
- .controller_address = 0x400e0a00,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_N,
+ .controller_address = 0x400e0A00,
+ .flash_wait_states = 6, /* workaround silicon bug */
.present = 1,
- .size_bytes = 128 * 1024,
- .nsectors = 16,
- .sector_size = 8192,
+ .size_bytes = 64 * 1024,
+ .nsectors = 4,
+ .sector_size = 16384,
.page_size = 256,
},
+
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+ },
},
},
{
- .chipid_cidr = 0x280a0760,
- .name = "at91sam3u2c",
- .total_flash_size = 128 * 1024,
- .total_sram_size = 36 * 1024,
- .n_gpnvms = 2,
+ .chipid_cidr = 0x29480560,
+ .name = "at91sam3n1b",
+ .total_flash_size = 64 * 1024,
+ .total_sram_size = 8 * 1024,
+ .n_gpnvms = 3,
.n_banks = 1,
// System boots at address 0x0
// boot is via FLASH
// Selection is via gpnvm[2]
// endif
- {
+ //
+ // NOTE: banks 0 & 1 switch places
+ // if gpnvm[2] == 0
+ // Bank0 is the boot rom
+ // else
+ // Bank1 is the boot rom
+ // endif
// .bank[0] = {
+ {
{
.probed = 0,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
- .base_address = FLASH_BANK0_BASE,
- .controller_address = 0x400e0800,
+ .base_address = FLASH_BANK_BASE_N,
+ .controller_address = 0x400e0A00,
+ .flash_wait_states = 6, /* workaround silicon bug */
.present = 1,
- .size_bytes = 128 * 1024,
- .nsectors = 16,
- .sector_size = 8192,
+ .size_bytes = 64 * 1024,
+ .nsectors = 4,
+ .sector_size = 16384,
.page_size = 256,
},
+
// .bank[1] = {
{
- .present = 0,
+ .present = 0,
.probed = 0,
.bank_number = 1,
},
},
},
+
{
- .chipid_cidr = 0x28090560,
- .name = "at91sam3u1c",
+ .chipid_cidr = 0x29380560,
+ .name = "at91sam3n1a",
.total_flash_size = 64 * 1024,
- .total_sram_size = 20 * 1024,
- .n_gpnvms = 2,
+ .total_sram_size = 8 * 1024,
+ .n_gpnvms = 3,
.n_banks = 1,
// System boots at address 0x0
// Selection is via gpnvm[2]
// endif
//
-
- {
+ // NOTE: banks 0 & 1 switch places
+ // if gpnvm[2] == 0
+ // Bank0 is the boot rom
+ // else
+ // Bank1 is the boot rom
+ // endif
// .bank[0] = {
+ {
{
.probed = 0,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
- .base_address = FLASH_BANK0_BASE,
- .controller_address = 0x400e0800,
+ .base_address = FLASH_BANK_BASE_N,
+ .controller_address = 0x400e0A00,
+ .flash_wait_states = 6, /* workaround silicon bug */
.present = 1,
- .size_bytes = 64 * 1024,
- .nsectors = 8,
- .sector_size = 8192,
+ .size_bytes = 64 * 1024,
+ .nsectors = 4,
+ .sector_size = 16384,
.page_size = 256,
},
+
// .bank[1] = {
{
- .present = 0,
+ .present = 0,
.probed = 0,
.bank_number = 1,
-
},
},
},
/****** END SAM3 CODE ********/
/* begin helpful debug code */
-
-static void
-sam3_sprintf(struct sam3_chip *pChip , const char *fmt, ...)
-{
- va_list ap;
- va_start(ap,fmt);
- if (pChip->mbuf == NULL) {
- return;
- }
-
- membuf_vsprintf(pChip->mbuf, fmt, ap);
- va_end(ap);
-}
-
// print the fieldname, the field value, in dec & hex, and return field value
static uint32_t
sam3_reg_fieldname(struct sam3_chip *pChip,
}
// show the basics
- sam3_sprintf(pChip, "\t%*s: %*d [0x%0*x] ",
+ LOG_USER_N("\t%*s: %*d [0x%0*x] ",
REG_NAME_WIDTH, regname,
dwidth, v,
hwidth, v);
uint32_t rcen;
v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
- sam3_sprintf(pChip, "(main xtal enabled: %s)\n",
+ LOG_USER("(main xtal enabled: %s)",
_yes_or_no(v));
v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
- sam3_sprintf(pChip, "(main osc bypass: %s)\n",
+ LOG_USER("(main osc bypass: %s)",
_yes_or_no(v));
- rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
- sam3_sprintf(pChip, "(onchip RC-OSC enabled: %s)\n",
+ rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
+ LOG_USER("(onchip RC-OSC enabled: %s)",
_yes_or_no(rcen));
v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
- sam3_sprintf(pChip, "(onchip RC-OSC freq: %s)\n",
+ LOG_USER("(onchip RC-OSC freq: %s)",
_rc_freq[v]);
pChip->cfg.rc_freq = 0;
switch (v) {
default:
pChip->cfg.rc_freq = 0;
+ break;
case 0:
pChip->cfg.rc_freq = 4 * 1000 * 1000;
break;
}
v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
- sam3_sprintf(pChip, "(startup clks, time= %f uSecs)\n",
+ LOG_USER("(startup clks, time= %f uSecs)",
((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
- sam3_sprintf(pChip, "(mainosc source: %s)\n",
+ LOG_USER("(mainosc source: %s)",
v ? "external xtal" : "internal RC");
v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
- sam3_sprintf(pChip, "(clock failure enabled: %s)\n",
+ LOG_USER("(clock failure enabled: %s)",
_yes_or_no(v));
}
const char *cp;
sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
- sam3_sprintf(pChip,"\n");
+ LOG_USER_N("\n");
v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
- sam3_sprintf(pChip, "%s\n", eproc_names[v]);
+ LOG_USER("%s", eproc_names[v]);
v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
- sam3_sprintf(pChip, "%s\n", nvpsize[v]);
+ LOG_USER("%s", nvpsize[v]);
v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
- sam3_sprintf(pChip, "%s\n", nvpsize2[v]);
+ LOG_USER("%s", nvpsize2[v]);
v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
- sam3_sprintf(pChip, "%s\n", sramsize[ v ]);
+ LOG_USER("%s", sramsize[ v ]);
v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
cp = _unknown;
}
}
- sam3_sprintf(pChip, "%s\n", cp);
+ LOG_USER("%s", cp);
v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
- sam3_sprintf(pChip, "%s\n", nvptype[ v ]);
+ LOG_USER("%s", nvptype[ v ]);
v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
- sam3_sprintf(pChip, "(exists: %s)\n", _yes_or_no(v));
+ LOG_USER("(exists: %s)", _yes_or_no(v));
}
static void
v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
- sam3_sprintf(pChip, "(main ready: %s)\n", _yes_or_no(v));
+ LOG_USER("(main ready: %s)", _yes_or_no(v));
v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
v = (v * pChip->cfg.slow_freq) / 16;
pChip->cfg.mainosc_freq = v;
- sam3_sprintf(pChip, "(%3.03f Mhz (%d.%03dkhz slowclk)\n",
+ LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
_tomhz(v),
pChip->cfg.slow_freq / 1000,
pChip->cfg.slow_freq % 1000);
uint32_t mula,diva;
diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
- sam3_sprintf(pChip,"\n");
+ LOG_USER_N("\n");
mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
- sam3_sprintf(pChip,"\n");
+ LOG_USER_N("\n");
pChip->cfg.plla_freq = 0;
if (mula == 0) {
- sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,mula = 0)\n");
+ LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
} else if (diva == 0) {
- sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,diva = 0)\n");
+ LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
} else if (diva == 1) {
pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
- sam3_sprintf(pChip,"\tPLLA Freq: %3.03f MHz\n",
+ LOG_USER("\tPLLA Freq: %3.03f MHz",
_tomhz(pChip->cfg.plla_freq));
}
}
break;
}
- sam3_sprintf(pChip, "%s (%3.03f Mhz)\n",
+ LOG_USER("%s (%3.03f Mhz)",
cp,
_tomhz(fin));
pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
case 0:
pdiv = 1;
cp = "selected clock";
+ break;
case 1:
pdiv = 2;
cp = "clock/2";
assert(0);
break;
}
- sam3_sprintf(pChip, "(%s)\n", cp);
+ LOG_USER("(%s)", cp);
fin = fin / pdiv;
// sam3 has a *SINGLE* clock -
// other at91 series parts have divisors for these.
pChip->cfg.cpu_freq = fin;
pChip->cfg.mclk_freq = fin;
pChip->cfg.fclk_freq = fin;
- sam3_sprintf(pChip, "\t\tResult CPU Freq: %3.03f\n",
+ LOG_USER("\t\tResult CPU Freq: %3.03f",
_tomhz(fin));
}
// By using prototypes - we can detect what would
// be casting errors.
- return ((uint32_t *)(((char *)(pCfg)) + pList->struct_offset));
+ return ((uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset));
}
// calculate where this one go..
// it is "possibly" this register.
- pPossible = ((uint32_t *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
+ pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
// well? Is it this register
if (pPossible == goes_here) {
r = target_read_u32(pChip->target, pReg->address, goes_here);
if (r != ERROR_OK) {
- LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
+ LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
pReg->name, (unsigned)(pReg->address), r);
}
return r;
r = sam3_ReadThisReg(pChip,
sam3_get_reg_ptr(&(pChip->cfg), pReg));
if (r != ERROR_OK) {
- LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
+ LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
pReg->name, ((unsigned)(pReg->address)), r);
return r;
}
const struct sam3_reg_list *pReg;
uint32_t regval;
- membuf_reset(pChip->mbuf);
-
-
pReg = &(sam3_all_regs[0]);
while (pReg->name) {
// display all regs
LOG_DEBUG("Start: %s", pReg->name);
regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
- sam3_sprintf(pChip, "%*s: [0x%08x] -> 0x%08x\n",
+ LOG_USER("%*s: [0x%08x] -> 0x%08x",
REG_NAME_WIDTH,
pReg->name,
pReg->address,
LOG_DEBUG("End: %s", pReg->name);
pReg++;
}
- sam3_sprintf(pChip," rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
- sam3_sprintf(pChip," mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
- sam3_sprintf(pChip," plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
- sam3_sprintf(pChip," cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
- sam3_sprintf(pChip,"mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
+ LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
+ LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
+ LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
+ LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
+ LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
- sam3_sprintf(pChip, " UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
pChip->cfg.unique_id[0],
pChip->cfg.unique_id[1],
pChip->cfg.unique_id[2],
return ERROR_TARGET_NOT_HALTED;
}
if (0 == bank->num_sectors) {
- LOG_ERROR("Target: not supported/not probed\n");
+ LOG_ERROR("Target: not supported/not probed");
return ERROR_FAIL;
}
// assumption is this runs at 32khz
pChip->cfg.slow_freq = 32768;
pChip->probed = 0;
- pChip->mbuf = membuf_new();
- if (!(pChip->mbuf)) {
- LOG_ERROR("no memory");
- return ERROR_FAIL;
- }
}
switch (bank->base) {
default:
- LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x)",
+ LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x \
+ [at91sam3u series] or 0x%08x [at91sam3s series] or \
+ 0x%08x [at91sam3n series])",
((unsigned int)(bank->base)),
- ((unsigned int)(FLASH_BANK0_BASE)),
- ((unsigned int)(FLASH_BANK1_BASE)));
+ ((unsigned int)(FLASH_BANK0_BASE_U)),
+ ((unsigned int)(FLASH_BANK1_BASE_U)),
+ ((unsigned int)(FLASH_BANK_BASE_S)),
+ ((unsigned int)(FLASH_BANK_BASE_N)));
return ERROR_FAIL;
break;
- case FLASH_BANK0_BASE:
+
+ // at91sam3u series
+ case FLASH_BANK0_BASE_U:
bank->driver_priv = &(pChip->details.bank[0]);
bank->bank_number = 0;
pChip->details.bank[0].pChip = pChip;
pChip->details.bank[0].pBank = bank;
break;
- case FLASH_BANK1_BASE:
+ case FLASH_BANK1_BASE_U:
bank->driver_priv = &(pChip->details.bank[1]);
bank->bank_number = 1;
pChip->details.bank[1].pChip = pChip;
pChip->details.bank[1].pBank = bank;
break;
+
+ /* at91sam3s and at91sam3n series */
+ case FLASH_BANK_BASE_S:
+ bank->driver_priv = &(pChip->details.bank[0]);
+ bank->bank_number = 0;
+ pChip->details.bank[0].pChip = pChip;
+ pChip->details.bank[0].pBank = bank;
+ break;
}
// we initialize after probing.
{
const struct sam3_chip_details *pDetails;
struct sam3_chip *pChip;
- void *vp;
struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
-
unsigned x;
- const char *cp;
LOG_DEBUG("Begin");
pDetails = all_sam3_details;
while (pDetails->name) {
- if (pDetails->chipid_cidr == pPrivate->pChip->cfg.CHIPID_CIDR) {
+ // Compare cidr without version bits
+ if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0)) {
break;
} else {
pDetails++;
LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
(unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
// Help the victim, print details about the chip
- membuf_reset(pPrivate->pChip->mbuf);
- membuf_sprintf(pPrivate->pChip->mbuf,
- "SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
+ LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
pPrivate->pChip->cfg.CHIPID_CIDR);
sam3_explain_chipid_cidr(pPrivate->pChip);
- cp = membuf_strtok(pPrivate->pChip->mbuf, "\n", &vp);
- while (cp) {
- LOG_INFO("%s", cp);
- cp = membuf_strtok(NULL, "\n", &vp);
- }
return ERROR_FAIL;
}
pPrivate = get_sam3_bank_private(bank);
if (!pPrivate) {
- LOG_ERROR("Invalid/unknown bank number\n");
+ LOG_ERROR("Invalid/unknown bank number");
return ERROR_FAIL;
}
LOG_DEBUG("Here");
- r = sam3_GetInfo(pPrivate->pChip);
+ if (pPrivate->pChip->probed) {
+ r = sam3_GetInfo(pPrivate->pChip);
+ } else {
+ r = sam3_GetDetails(pPrivate);
+ }
if (r != ERROR_OK) {
return r;
}
- if (!(pPrivate->pChip->probed)) {
- pPrivate->pChip->probed = 1;
- LOG_DEBUG("Here");
- r = sam3_GetDetails(pPrivate);
- if (r != ERROR_OK) {
- return r;
- }
- }
// update the flash bank size
for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
- if (bank->base == pPrivate->pChip->details.bank[0].base_address) {
- bank->size = pPrivate->pChip->details.bank[0].size_bytes;
+ if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
+ bank->size = pPrivate->pChip->details.bank[x].size_bytes;
break;
}
}
{
uint32_t adr;
uint32_t status;
+ uint32_t fmr; /* EEFC Flash Mode Register */
int r;
adr = pagenum * pPrivate->page_size;
adr += (adr + pPrivate->base_address);
+ /* Get flash mode register value */
+ r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
+ if (r != ERROR_OK)
+ LOG_DEBUG("Error Read failed: read flash mode register");
+
+ /* Clear flash wait state field */
+ fmr &= 0xfffff0ff;
+
+ /* set FWS (flash wait states) field in the FMR (flash mode register) */
+ fmr |= (pPrivate->flash_wait_states << 8);
+
+ LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
+ r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
+ if (r != ERROR_OK)
+ LOG_DEBUG("Error Write failed: set flash mode register");
+
LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
r = target_write_memory(pPrivate->pChip->target,
adr,
page_cur++;
}
+ /* By checking that offset is correct here, we also
+ fix a clang warning */
+ assert(offset == pPrivate->page_size);
+
// intermediate large pages
// also - the final *terminal*
// if that terminal page is a full page
goto done;
}
buffer += count;
- count -= count;
}
LOG_DEBUG("Done!");
r = ERROR_OK;
COMMAND_HANDLER(sam3_handle_info_command)
{
struct sam3_chip *pChip;
- void *vp;
- const char *cp;
- unsigned x;
- int r;
-
pChip = get_current_sam3(CMD_CTX);
if (!pChip) {
return ERROR_OK;
}
- r = 0;
+ unsigned x;
+ int r;
// bank0 must exist before we can do anything
if (pChip->details.bank[0].pBank == NULL) {
r = sam3_GetInfo(pChip);
if (r != ERROR_OK) {
- LOG_DEBUG("Sam3Info, Failed %d\n",r);
+ LOG_DEBUG("Sam3Info, Failed %d",r);
return r;
}
-
- // print results
- cp = membuf_strtok(pChip->mbuf, "\n", &vp);
- while (cp) {
- command_print(CMD_CTX,"%s", cp);
- cp = membuf_strtok(NULL, "\n", &vp);
- }
return ERROR_OK;
}
}
}
-
switch (CMD_ARGC) {
default:
- command_print(CMD_CTX,"Too many parameters\n");
return ERROR_COMMAND_SYNTAX_ERROR;
break;
case 0:
- who = -1;
goto showall;
break;
case 1:
(0 == strcmp("clear", CMD_ARGV[0]))) { // quietly accept both
r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
} else {
- command_print(CMD_CTX, "Unkown command: %s", CMD_ARGV[0]);
+ command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
r = ERROR_COMMAND_SYNTAX_ERROR;
}
return r;
.name = "at91sam3",
.mode = COMMAND_ANY,
.help = "at91sam3 flash command group",
+ .usage = "",
.chain = at91sam3_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
projects / fw / openocd / blobdiff