#define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
#define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
-#define offset_EFC_FMR 0
-#define offset_EFC_FCR 4
-#define offset_EFC_FSR 8
-#define offset_EFC_FRR 12
+#define OFFSET_EFC_FMR 0
+#define OFFSET_EFC_FCR 4
+#define OFFSET_EFC_FSR 8
+#define OFFSET_EFC_FRR 12
extern const struct flash_driver at91sam3_flash;
/* DANGER: THERE ARE DRAGONS HERE.. */
/* NOTE: If you add more 'ghost' pointers */
/* be aware that you must *manually* update */
- /* these pointers in the function sam3_GetDetails() */
+ /* these pointers in the function sam3_get_details() */
/* See the comment "Here there be dragons" */
/* so we can find the chip we belong to */
- struct sam3_chip *pChip;
+ struct sam3_chip *chip;
/* so we can find the original bank pointer */
- struct flash_bank *pBank;
+ struct flash_bank *bank;
unsigned bank_number;
uint32_t controller_address;
uint32_t base_address;
/* note: If you add pointers here */
/* be careful about them as they */
/* may need to be updated inside */
- /* the function: "sam3_GetDetails() */
+ /* the function: "sam3_get_details() */
/* which copy/overwrites the */
/* 'runtime' copy of this structure */
uint32_t chipid_cidr;
struct sam3_reg_list {
uint32_t address; size_t struct_offset; const char *name;
- void (*explain_func)(struct sam3_chip *pInfo);
+ void (*explain_func)(struct sam3_chip *chip);
};
static struct sam3_chip *all_sam3_chips;
return NULL;
}
-/* these are used to *initialize* the "pChip->details" structure. */
+/* these are used to *initialize* the "chip->details" structure. */
static const struct sam3_chip_details all_sam3_details[] = {
/* Start at91sam3u* series */
{
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_U,
.controller_address = 0x400e0a00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
{
/* .bank[0] = { */
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_U,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_256K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_256K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_256K_AX,
.controller_address = 0x400e0c00,
/**
* Get the current status of the EEFC and
* the value of some status bits (LOCKE, PROGE).
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param v - result goes here
*/
-static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int efc_get_status(struct sam3_bank_private *private, uint32_t *v)
{
int r;
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->controller_address + offset_EFC_FSR,
+ r = target_read_u32(private->chip->target,
+ private->controller_address + OFFSET_EFC_FSR,
v);
LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
(unsigned int)(*v),
/**
* Get the result of the last executed command.
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param v - result goes here
*/
-static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int efc_get_result(struct sam3_bank_private *private, uint32_t *v)
{
int r;
uint32_t rv;
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->controller_address + offset_EFC_FRR,
+ r = target_read_u32(private->chip->target,
+ private->controller_address + OFFSET_EFC_FRR,
&rv);
if (v)
*v = rv;
return r;
}
-static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
+static int efc_start_command(struct sam3_bank_private *private,
unsigned command, unsigned argument)
{
uint32_t n, v;
/* case AT91C_EFC_FCMD_EPA: */
case AT91C_EFC_FCMD_SLB:
case AT91C_EFC_FCMD_CLB:
- n = (pPrivate->size_bytes / pPrivate->page_size);
+ n = (private->size_bytes / private->page_size);
if (argument >= n)
LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
break;
case AT91C_EFC_FCMD_SFB:
case AT91C_EFC_FCMD_CFB:
- if (argument >= pPrivate->pChip->details.n_gpnvms) {
+ if (argument >= private->chip->details.n_gpnvms) {
LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
- pPrivate->pChip->details.n_gpnvms);
+ private->chip->details.n_gpnvms);
}
break;
/* Situation (2) - normal, finished reading unique id */
} else {
/* it should be "ready" */
- EFC_GetStatus(pPrivate, &v);
+ efc_get_status(private, &v);
if (v & 1) {
/* then it is ready */
/* we go on */
/* we have done this before */
/* the controller is not responding. */
LOG_ERROR("flash controller(%d) is not ready! Error",
- pPrivate->bank_number);
+ private->bank_number);
return ERROR_FAIL;
} else {
retry++;
LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
- pPrivate->bank_number);
+ private->bank_number);
/* we do that by issuing the *STOP* command */
- EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
+ efc_start_command(private, AT91C_EFC_FCMD_SPUI, 0);
/* above is recursive, and further recursion is blocked by */
/* if (command == AT91C_EFC_FCMD_SPUI) above */
goto do_retry;
v = (0x5A << 24) | (argument << 8) | command;
LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
- r = target_write_u32(pPrivate->pBank->target,
- pPrivate->controller_address + offset_EFC_FCR, v);
+ r = target_write_u32(private->bank->target,
+ private->controller_address + OFFSET_EFC_FCR, v);
if (r != ERROR_OK)
LOG_DEBUG("Error Write failed");
return r;
/**
* Performs the given command and wait until its completion (or an error).
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param command - Command to perform.
* @param argument - Optional command argument.
* @param status - put command status bits here
*/
-static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
+static int efc_perform_command(struct sam3_bank_private *private,
unsigned command,
unsigned argument,
uint32_t *status)
if (status)
*status = 0;
- r = EFC_StartCommand(pPrivate, command, argument);
+ r = efc_start_command(private, command, argument);
if (r != ERROR_OK)
return r;
ms_end = 500 + timeval_ms();
do {
- r = EFC_GetStatus(pPrivate, &v);
+ r = efc_get_status(private, &v);
if (r != ERROR_OK)
return r;
ms_now = timeval_ms();
/**
* Read the unique ID.
- * @param pPrivate - info about the bank
- * The unique ID is stored in the 'pPrivate' structure.
+ * @param private - info about the bank
+ * The unique ID is stored in the 'private' structure.
*/
-static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
+static int flashd_read_uid(struct sam3_bank_private *private)
{
int r;
uint32_t v;
int x;
/* assume 0 */
- pPrivate->pChip->cfg.unique_id[0] = 0;
- pPrivate->pChip->cfg.unique_id[1] = 0;
- pPrivate->pChip->cfg.unique_id[2] = 0;
- pPrivate->pChip->cfg.unique_id[3] = 0;
+ private->chip->cfg.unique_id[0] = 0;
+ private->chip->cfg.unique_id[1] = 0;
+ private->chip->cfg.unique_id[2] = 0;
+ private->chip->cfg.unique_id[3] = 0;
LOG_DEBUG("Begin");
- r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
+ r = efc_start_command(private, AT91C_EFC_FCMD_STUI, 0);
if (r < 0)
return r;
for (x = 0; x < 4; x++) {
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->pBank->base + (x * 4),
+ r = target_read_u32(private->chip->target,
+ private->bank->base + (x * 4),
&v);
if (r < 0)
return r;
- pPrivate->pChip->cfg.unique_id[x] = v;
+ private->chip->cfg.unique_id[x] = v;
}
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SPUI, 0, NULL);
LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
r,
- (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
+ (unsigned int)(private->chip->cfg.unique_id[0]),
+ (unsigned int)(private->chip->cfg.unique_id[1]),
+ (unsigned int)(private->chip->cfg.unique_id[2]),
+ (unsigned int)(private->chip->cfg.unique_id[3]));
return r;
}
/**
* Erases the entire flash.
- * @param pPrivate - the info about the bank.
+ * @param private - the info about the bank.
*/
-static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
+static int flashd_erase_entire_bank(struct sam3_bank_private *private)
{
LOG_DEBUG("Here");
- return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
+ return efc_perform_command(private, AT91C_EFC_FCMD_EA, 0, NULL);
}
/**
* Gets current GPNVM state.
- * @param pPrivate - info about the bank.
+ * @param private - info about the bank.
* @param gpnvm - GPNVM bit index.
* @param puthere - result stored here.
*/
/* ------------------------------------------------------------------------------ */
-static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
+static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned gpnvm, unsigned *puthere)
{
uint32_t v;
int r;
LOG_DEBUG("Here");
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
/* Get GPNVMs status */
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_GFB, 0, NULL);
if (r != ERROR_OK) {
LOG_ERROR("Failed");
return r;
}
- r = EFC_GetResult(pPrivate, &v);
+ r = efc_get_result(private, &v);
if (puthere) {
/* Check if GPNVM is set */
/**
* Clears the selected GPNVM bit.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param gpnvm GPNVM index.
* @returns 0 if successful; otherwise returns an error code.
*/
-static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
+static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned gpnvm)
{
int r;
unsigned v;
LOG_DEBUG("Here");
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
- r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
+ r = flashd_get_gpnvm(private, gpnvm, &v);
if (r != ERROR_OK) {
LOG_DEBUG("Failed: %d", r);
return r;
}
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
LOG_DEBUG("End: %d", r);
return r;
}
/**
* Sets the selected GPNVM bit.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param gpnvm GPNVM index.
*/
-static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
+static int flashd_set_gpnvm(struct sam3_bank_private *private, unsigned gpnvm)
{
int r;
unsigned v;
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
- r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
+ r = flashd_get_gpnvm(private, gpnvm, &v);
if (r != ERROR_OK)
return r;
if (v) {
r = ERROR_OK;
} else {
/* set it */
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
}
return r;
}
/**
* Returns a bit field (at most 64) of locked regions within a page.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param v where to store locked bits
*/
-static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int flashd_get_lock_bits(struct sam3_bank_private *private, uint32_t *v)
{
int r;
LOG_DEBUG("Here");
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_GLB, 0, NULL);
if (r == ERROR_OK)
- r = EFC_GetResult(pPrivate, v);
+ r = efc_get_result(private, v);
LOG_DEBUG("End: %d", r);
return r;
}
/**
* Unlocks all the regions in the given address range.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param start_sector first sector to unlock
* @param end_sector last (inclusive) to unlock
*/
-static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
+static int flashd_unlock(struct sam3_bank_private *private,
unsigned start_sector,
unsigned end_sector)
{
uint32_t pg;
uint32_t pages_per_sector;
- pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
+ pages_per_sector = private->sector_size / private->page_size;
/* Unlock all pages */
while (start_sector <= end_sector) {
pg = start_sector * pages_per_sector;
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_CLB, pg, &status);
if (r != ERROR_OK)
return r;
start_sector++;
/**
* Locks regions
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param start_sector - first sector to lock
* @param end_sector - last sector (inclusive) to lock
*/
-static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
+static int flashd_lock(struct sam3_bank_private *private,
unsigned start_sector,
unsigned end_sector)
{
uint32_t pages_per_sector;
int r;
- pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
+ pages_per_sector = private->sector_size / private->page_size;
/* Lock all pages */
while (start_sector <= end_sector) {
pg = start_sector * pages_per_sector;
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SLB, pg, &status);
if (r != ERROR_OK)
return r;
start_sector++;
/* begin helpful debug code */
/* print the fieldname, the field value, in dec & hex, and return field value */
-static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
+static uint32_t sam3_reg_fieldname(struct sam3_chip *chip,
const char *regname,
uint32_t value,
unsigned shift,
"4 MHz", "8 MHz", "12 MHz", "reserved"
};
-static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
+static void sam3_explain_ckgr_mor(struct sam3_chip *chip)
{
uint32_t v;
uint32_t rcen;
- v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
+ v = sam3_reg_fieldname(chip, "MOSCXTEN", chip->cfg.CKGR_MOR, 0, 1);
LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
- v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
+ v = sam3_reg_fieldname(chip, "MOSCXTBY", chip->cfg.CKGR_MOR, 1, 1);
LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
- rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
+ rcen = sam3_reg_fieldname(chip, "MOSCRCEN", chip->cfg.CKGR_MOR, 3, 1);
LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
- v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
+ v = sam3_reg_fieldname(chip, "MOSCRCF", chip->cfg.CKGR_MOR, 4, 3);
LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
- pChip->cfg.rc_freq = 0;
+ chip->cfg.rc_freq = 0;
if (rcen) {
switch (v) {
default:
- pChip->cfg.rc_freq = 0;
+ chip->cfg.rc_freq = 0;
break;
case 0:
- pChip->cfg.rc_freq = 4 * 1000 * 1000;
+ chip->cfg.rc_freq = 4 * 1000 * 1000;
break;
case 1:
- pChip->cfg.rc_freq = 8 * 1000 * 1000;
+ chip->cfg.rc_freq = 8 * 1000 * 1000;
break;
case 2:
- pChip->cfg.rc_freq = 12 * 1000 * 1000;
+ chip->cfg.rc_freq = 12 * 1000 * 1000;
break;
}
}
- v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
+ v = sam3_reg_fieldname(chip, "MOSCXTST", chip->cfg.CKGR_MOR, 8, 8);
LOG_USER("(startup clks, time= %f uSecs)",
- ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
- v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
+ ((float)(v * 1000000)) / ((float)(chip->cfg.slow_freq)));
+ v = sam3_reg_fieldname(chip, "MOSCSEL", chip->cfg.CKGR_MOR, 24, 1);
LOG_USER("(mainosc source: %s)",
v ? "external xtal" : "internal RC");
- v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
+ v = sam3_reg_fieldname(chip, "CFDEN", chip->cfg.CKGR_MOR, 25, 1);
LOG_USER("(clock failure enabled: %s)",
_yes_or_no(v));
}
-static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
+static void sam3_explain_chipid_cidr(struct sam3_chip *chip)
{
int x;
uint32_t v;
const char *cp;
- sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
+ sam3_reg_fieldname(chip, "Version", chip->cfg.CHIPID_CIDR, 0, 5);
LOG_USER_N("\n");
- v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
+ v = sam3_reg_fieldname(chip, "EPROC", chip->cfg.CHIPID_CIDR, 5, 3);
LOG_USER("%s", eproc_names[v]);
- v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
+ v = sam3_reg_fieldname(chip, "NVPSIZE", chip->cfg.CHIPID_CIDR, 8, 4);
LOG_USER("%s", nvpsize[v]);
- v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
+ v = sam3_reg_fieldname(chip, "NVPSIZE2", chip->cfg.CHIPID_CIDR, 12, 4);
LOG_USER("%s", nvpsize2[v]);
- v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
+ v = sam3_reg_fieldname(chip, "SRAMSIZE", chip->cfg.CHIPID_CIDR, 16, 4);
LOG_USER("%s", sramsize[v]);
- v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
+ v = sam3_reg_fieldname(chip, "ARCH", chip->cfg.CHIPID_CIDR, 20, 8);
cp = _unknown;
for (x = 0; archnames[x].name; x++) {
if (v == archnames[x].value) {
LOG_USER("%s", cp);
- v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
+ v = sam3_reg_fieldname(chip, "NVPTYP", chip->cfg.CHIPID_CIDR, 28, 3);
LOG_USER("%s", nvptype[v]);
- v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
+ v = sam3_reg_fieldname(chip, "EXTID", chip->cfg.CHIPID_CIDR, 31, 1);
LOG_USER("(exists: %s)", _yes_or_no(v));
}
-static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
+static void sam3_explain_ckgr_mcfr(struct sam3_chip *chip)
{
uint32_t v;
- v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
+ v = sam3_reg_fieldname(chip, "MAINFRDY", chip->cfg.CKGR_MCFR, 16, 1);
LOG_USER("(main ready: %s)", _yes_or_no(v));
- v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
+ v = sam3_reg_fieldname(chip, "MAINF", chip->cfg.CKGR_MCFR, 0, 16);
- v = (v * pChip->cfg.slow_freq) / 16;
- pChip->cfg.mainosc_freq = v;
+ v = (v * chip->cfg.slow_freq) / 16;
+ chip->cfg.mainosc_freq = v;
LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
_tomhz(v),
- (uint32_t)(pChip->cfg.slow_freq / 1000),
- (uint32_t)(pChip->cfg.slow_freq % 1000));
+ (uint32_t)(chip->cfg.slow_freq / 1000),
+ (uint32_t)(chip->cfg.slow_freq % 1000));
}
-static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
+static void sam3_explain_ckgr_plla(struct sam3_chip *chip)
{
uint32_t mula, diva;
- diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
+ diva = sam3_reg_fieldname(chip, "DIVA", chip->cfg.CKGR_PLLAR, 0, 8);
LOG_USER_N("\n");
- mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
+ mula = sam3_reg_fieldname(chip, "MULA", chip->cfg.CKGR_PLLAR, 16, 11);
LOG_USER_N("\n");
- pChip->cfg.plla_freq = 0;
+ chip->cfg.plla_freq = 0;
if (mula == 0)
LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
else if (diva == 0)
LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
else if (diva >= 1) {
- pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
+ chip->cfg.plla_freq = (chip->cfg.mainosc_freq * (mula + 1) / diva);
LOG_USER("\tPLLA Freq: %3.03f MHz",
- _tomhz(pChip->cfg.plla_freq));
+ _tomhz(chip->cfg.plla_freq));
}
}
-static void sam3_explain_mckr(struct sam3_chip *pChip)
+static void sam3_explain_mckr(struct sam3_chip *chip)
{
uint32_t css, pres, fin = 0;
int pdiv = 0;
const char *cp = NULL;
- css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
+ css = sam3_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2);
switch (css & 3) {
case 0:
- fin = pChip->cfg.slow_freq;
+ fin = chip->cfg.slow_freq;
cp = "slowclk";
break;
case 1:
- fin = pChip->cfg.mainosc_freq;
+ fin = chip->cfg.mainosc_freq;
cp = "mainosc";
break;
case 2:
- fin = pChip->cfg.plla_freq;
+ fin = chip->cfg.plla_freq;
cp = "plla";
break;
case 3:
- if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
+ if (chip->cfg.CKGR_UCKR & (1 << 16)) {
fin = 480 * 1000 * 1000;
cp = "upll";
} else {
LOG_USER("%s (%3.03f Mhz)",
cp,
_tomhz(fin));
- pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
+ pres = sam3_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3);
switch (pres & 0x07) {
case 0:
pdiv = 1;
fin = fin / pdiv;
/* sam3 has a *SINGLE* clock - */
/* other at91 series parts have divisors for these. */
- pChip->cfg.cpu_freq = fin;
- pChip->cfg.mclk_freq = fin;
- pChip->cfg.fclk_freq = fin;
+ chip->cfg.cpu_freq = fin;
+ chip->cfg.mclk_freq = fin;
+ chip->cfg.fclk_freq = fin;
LOG_USER("\t\tResult CPU Freq: %3.03f",
_tomhz(fin));
}
#if 0
-static struct sam3_chip *target2sam3(struct target *pTarget)
+static struct sam3_chip *target2sam3(struct target *target)
{
- struct sam3_chip *pChip;
+ struct sam3_chip *chip;
- if (pTarget == NULL)
+ if (target == NULL)
return NULL;
- pChip = all_sam3_chips;
- while (pChip) {
- if (pChip->target == pTarget)
+ chip = all_sam3_chips;
+ while (chip) {
+ if (chip->target == target)
break; /* return below */
else
- pChip = pChip->next;
+ chip = chip->next;
}
- return pChip;
+ return chip;
}
#endif
-static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
+static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *cfg, const struct sam3_reg_list *list)
{
/* this function exists to help */
/* keep funky offsetof() errors */
/* By using prototypes - we can detect what would */
/* be casting errors. */
- return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
+ return (uint32_t *)(void *)(((char *)(cfg)) + list->struct_offset);
}
* Given a pointer to where it goes in the structure,
* determine the register name, address from the all registers table.
*/
-static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
+static const struct sam3_reg_list *sam3_get_reg(struct sam3_chip *chip, uint32_t *goes_here)
{
- const struct sam3_reg_list *pReg;
+ const struct sam3_reg_list *reg;
- pReg = &(sam3_all_regs[0]);
- while (pReg->name) {
- uint32_t *pPossible;
+ reg = &(sam3_all_regs[0]);
+ while (reg->name) {
+ uint32_t *possible;
/* calculate where this one go.. */
/* it is "possibly" this register. */
- pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
+ possible = ((uint32_t *)(void *)(((char *)(&(chip->cfg))) + reg->struct_offset));
/* well? Is it this register */
- if (pPossible == goes_here) {
+ if (possible == goes_here) {
/* Jump for joy! */
- return pReg;
+ return reg;
}
/* next... */
- pReg++;
+ reg++;
}
/* This is *TOTAL*PANIC* - we are totally screwed. */
LOG_ERROR("INVALID SAM3 REGISTER");
return NULL;
}
-static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
+static int sam3_read_this_reg(struct sam3_chip *chip, uint32_t *goes_here)
{
- const struct sam3_reg_list *pReg;
+ const struct sam3_reg_list *reg;
int r;
- pReg = sam3_GetReg(pChip, goes_here);
- if (!pReg)
+ reg = sam3_get_reg(chip, goes_here);
+ if (!reg)
return ERROR_FAIL;
- r = target_read_u32(pChip->target, pReg->address, goes_here);
+ r = target_read_u32(chip->target, reg->address, goes_here);
if (r != ERROR_OK) {
LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
- pReg->name, (unsigned)(pReg->address), r);
+ reg->name, (unsigned)(reg->address), r);
}
return r;
}
-static int sam3_ReadAllRegs(struct sam3_chip *pChip)
+static int sam3_read_all_regs(struct sam3_chip *chip)
{
int r;
- const struct sam3_reg_list *pReg;
+ const struct sam3_reg_list *reg;
- pReg = &(sam3_all_regs[0]);
- while (pReg->name) {
- r = sam3_ReadThisReg(pChip,
- sam3_get_reg_ptr(&(pChip->cfg), pReg));
+ reg = &(sam3_all_regs[0]);
+ while (reg->name) {
+ r = sam3_read_this_reg(chip,
+ sam3_get_reg_ptr(&(chip->cfg), reg));
if (r != ERROR_OK) {
LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
- pReg->name, ((unsigned)(pReg->address)), r);
+ reg->name, ((unsigned)(reg->address)), r);
return r;
}
- pReg++;
+ reg++;
}
/* Chip identification register
* located in the memory map of the Power Management Controller
* (PMC). Furthermore, the address is not used by the PMC.
* So when read, the memory controller returns zero.*/
- if (pChip->cfg.CHIPID_CIDR == 0) {
- /*Put the correct CIDR and EXID values in the pChip structure */
- pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;
- pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;
+ if (chip->cfg.CHIPID_CIDR == 0) {
+ /*Put the correct CIDR and EXID values in the chip structure */
+ chip->cfg.CHIPID_CIDR = chip->cfg.CHIPID_CIDR2;
+ chip->cfg.CHIPID_EXID = chip->cfg.CHIPID_EXID2;
}
return ERROR_OK;
}
-static int sam3_GetInfo(struct sam3_chip *pChip)
+static int sam3_get_info(struct sam3_chip *chip)
{
- const struct sam3_reg_list *pReg;
+ const struct sam3_reg_list *reg;
uint32_t regval;
- pReg = &(sam3_all_regs[0]);
- while (pReg->name) {
+ reg = &(sam3_all_regs[0]);
+ while (reg->name) {
/* display all regs */
- LOG_DEBUG("Start: %s", pReg->name);
- regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
+ LOG_DEBUG("Start: %s", reg->name);
+ regval = *sam3_get_reg_ptr(&(chip->cfg), reg);
LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
REG_NAME_WIDTH,
- pReg->name,
- pReg->address,
+ reg->name,
+ reg->address,
regval);
- if (pReg->explain_func)
- (*(pReg->explain_func))(pChip);
- LOG_DEBUG("End: %s", pReg->name);
- pReg++;
+ if (reg->explain_func)
+ (*(reg->explain_func))(chip);
+ LOG_DEBUG("End: %s", reg->name);
+ reg++;
}
- LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
- LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
- LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
- LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
- LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
+ LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip->cfg.rc_freq));
+ LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip->cfg.mainosc_freq));
+ LOG_USER(" plla: %3.03f MHz", _tomhz(chip->cfg.plla_freq));
+ LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip->cfg.cpu_freq));
+ LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip->cfg.mclk_freq));
LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32,
- pChip->cfg.unique_id[0],
- pChip->cfg.unique_id[1],
- pChip->cfg.unique_id[2],
- pChip->cfg.unique_id[3]);
+ chip->cfg.unique_id[0],
+ chip->cfg.unique_id[1],
+ chip->cfg.unique_id[2],
+ chip->cfg.unique_id[3]);
return ERROR_OK;
}
int r;
uint32_t v = 0;
unsigned x;
- struct sam3_bank_private *pPrivate;
+ struct sam3_bank_private *private;
LOG_DEBUG("Begin");
if (bank->target->state != TARGET_HALTED) {
return ERROR_TARGET_NOT_HALTED;
}
- pPrivate = get_sam3_bank_private(bank);
- if (!pPrivate) {
+ private = get_sam3_bank_private(bank);
+ if (!private) {
LOG_ERROR("no private for this bank?");
return ERROR_FAIL;
}
- if (!(pPrivate->probed))
+ if (!(private->probed))
return ERROR_FLASH_BANK_NOT_PROBED;
- r = FLASHD_GetLockBits(pPrivate, &v);
+ r = flashd_get_lock_bits(private, &v);
if (r != ERROR_OK) {
LOG_DEBUG("Failed: %d", r);
return r;
}
- for (x = 0; x < pPrivate->nsectors; x++)
+ for (x = 0; x < private->nsectors; x++)
bank->sectors[x].is_protected = (!!(v & (1 << x)));
LOG_DEBUG("Done");
return ERROR_OK;
FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
{
- struct sam3_chip *pChip;
+ struct sam3_chip *chip;
- pChip = all_sam3_chips;
+ chip = all_sam3_chips;
/* is this an existing chip? */
- while (pChip) {
- if (pChip->target == bank->target)
+ while (chip) {
+ if (chip->target == bank->target)
break;
- pChip = pChip->next;
+ chip = chip->next;
}
- if (!pChip) {
+ if (!chip) {
/* this is a *NEW* chip */
- pChip = calloc(1, sizeof(struct sam3_chip));
- if (!pChip) {
+ chip = calloc(1, sizeof(struct sam3_chip));
+ if (!chip) {
LOG_ERROR("NO RAM!");
return ERROR_FAIL;
}
- pChip->target = bank->target;
+ chip->target = bank->target;
/* insert at head */
- pChip->next = all_sam3_chips;
- all_sam3_chips = pChip;
- pChip->target = bank->target;
+ chip->next = all_sam3_chips;
+ all_sam3_chips = chip;
+ chip->target = bank->target;
/* assumption is this runs at 32khz */
- pChip->cfg.slow_freq = 32768;
- pChip->probed = false;
+ chip->cfg.slow_freq = 32768;
+ chip->probed = false;
}
switch (bank->base) {
/* at91sam3u and at91sam3ax series has the same address for bank 0*/
case FLASH_BANK_BASE_S:
case FLASH_BANK0_BASE_U:
- bank->driver_priv = &(pChip->details.bank[0]);
+ bank->driver_priv = &(chip->details.bank[0]);
bank->bank_number = 0;
- pChip->details.bank[0].pChip = pChip;
- pChip->details.bank[0].pBank = bank;
+ chip->details.bank[0].chip = chip;
+ chip->details.bank[0].bank = bank;
break;
/* Bank 1 of at91sam3u or at91sam3ax series */
case FLASH_BANK1_BASE_U:
case FLASH_BANK1_BASE_256K_AX:
case FLASH_BANK1_BASE_512K_AX:
- bank->driver_priv = &(pChip->details.bank[1]);
+ bank->driver_priv = &(chip->details.bank[1]);
bank->bank_number = 1;
- pChip->details.bank[1].pChip = pChip;
- pChip->details.bank[1].pBank = bank;
+ chip->details.bank[1].chip = chip;
+ chip->details.bank[1].bank = bank;
break;
}
all_sam3_chips = NULL;
}
-static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
+static int sam3_get_details(struct sam3_bank_private *private)
{
- const struct sam3_chip_details *pDetails;
- struct sam3_chip *pChip;
+ const struct sam3_chip_details *details;
+ struct sam3_chip *chip;
struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
unsigned x;
LOG_DEBUG("Begin");
- pDetails = all_sam3_details;
- while (pDetails->name) {
+ details = all_sam3_details;
+ while (details->name) {
/* Compare cidr without version bits */
- if (((pDetails->chipid_cidr ^ pPrivate->pChip->cfg.CHIPID_CIDR) & 0xFFFFFFE0) == 0)
+ if (((details->chipid_cidr ^ private->chip->cfg.CHIPID_CIDR) & 0xFFFFFFE0) == 0)
break;
else
- pDetails++;
+ details++;
}
- if (pDetails->name == NULL) {
+ if (details->name == NULL) {
LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
- (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
+ (unsigned int)(private->chip->cfg.CHIPID_CIDR));
/* Help the victim, print details about the chip */
LOG_INFO("SAM3 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
- pPrivate->pChip->cfg.CHIPID_CIDR);
- sam3_explain_chipid_cidr(pPrivate->pChip);
+ private->chip->cfg.CHIPID_CIDR);
+ sam3_explain_chipid_cidr(private->chip);
return ERROR_FAIL;
}
/* DANGER: THERE ARE DRAGONS HERE */
- /* get our pChip - it is going */
+ /* get our chip - it is going */
/* to be over-written shortly */
- pChip = pPrivate->pChip;
+ chip = private->chip;
/* Note that, in reality: */
/* */
- /* pPrivate = &(pChip->details.bank[0]) */
- /* or pPrivate = &(pChip->details.bank[1]) */
+ /* private = &(chip->details.bank[0]) */
+ /* or private = &(chip->details.bank[1]) */
/* */
/* save the "bank" pointers */
for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
- saved_banks[x] = pChip->details.bank[x].pBank;
+ saved_banks[x] = chip->details.bank[x].bank;
/* Overwrite the "details" structure. */
- memcpy(&(pPrivate->pChip->details),
- pDetails,
- sizeof(pPrivate->pChip->details));
+ memcpy(&(private->chip->details),
+ details,
+ sizeof(private->chip->details));
/* now fix the ghosted pointers */
for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
- pChip->details.bank[x].pChip = pChip;
- pChip->details.bank[x].pBank = saved_banks[x];
+ chip->details.bank[x].chip = chip;
+ chip->details.bank[x].bank = saved_banks[x];
}
/* update the *BANK*SIZE* */
static int _sam3_probe(struct flash_bank *bank, int noise)
{
int r;
- struct sam3_bank_private *pPrivate;
+ struct sam3_bank_private *private;
LOG_DEBUG("Begin: Bank: %u, Noise: %d", bank->bank_number, noise);
return ERROR_TARGET_NOT_HALTED;
}
- pPrivate = get_sam3_bank_private(bank);
- if (!pPrivate) {
+ private = get_sam3_bank_private(bank);
+ if (!private) {
LOG_ERROR("Invalid/unknown bank number");
return ERROR_FAIL;
}
- r = sam3_ReadAllRegs(pPrivate->pChip);
+ r = sam3_read_all_regs(private->chip);
if (r != ERROR_OK)
return r;
LOG_DEBUG("Here");
- if (pPrivate->pChip->probed)
- r = sam3_GetInfo(pPrivate->pChip);
+ if (private->chip->probed)
+ r = sam3_get_info(private->chip);
else
- r = sam3_GetDetails(pPrivate);
+ r = sam3_get_details(private);
if (r != ERROR_OK)
return r;
/* update the flash bank size */
for (unsigned int x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
- if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
- bank->size = pPrivate->pChip->details.bank[x].size_bytes;
+ if (bank->base == private->chip->details.bank[x].base_address) {
+ bank->size = private->chip->details.bank[x].size_bytes;
break;
}
}
if (bank->sectors == NULL) {
- bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
+ bank->sectors = calloc(private->nsectors, (sizeof((bank->sectors)[0])));
if (bank->sectors == NULL) {
LOG_ERROR("No memory!");
return ERROR_FAIL;
}
- bank->num_sectors = pPrivate->nsectors;
+ bank->num_sectors = private->nsectors;
for (unsigned int x = 0; x < bank->num_sectors; x++) {
- bank->sectors[x].size = pPrivate->sector_size;
- bank->sectors[x].offset = x * (pPrivate->sector_size);
+ bank->sectors[x].size = private->sector_size;
+ bank->sectors[x].offset = x * (private->sector_size);
/* mark as unknown */
bank->sectors[x].is_erased = -1;
bank->sectors[x].is_protected = -1;
}
}
- pPrivate->probed = true;
+ private->probed = true;
r = sam3_protect_check(bank);
if (r != ERROR_OK)
return r;
LOG_DEBUG("Bank = %d, nbanks = %d",
- pPrivate->bank_number, pPrivate->pChip->details.n_banks);
- if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
+ private->bank_number, private->chip->details.n_banks);
+ if ((private->bank_number + 1) == private->chip->details.n_banks) {
/* read unique id, */
/* it appears to be associated with the *last* flash bank. */
- FLASHD_ReadUniqueID(pPrivate);
+ flashd_read_uid(private);
}
return r;
static int sam3_erase(struct flash_bank *bank, unsigned int first,
unsigned int last)
{
- struct sam3_bank_private *pPrivate;
+ struct sam3_bank_private *private;
int r;
LOG_DEBUG("Here");
return r;
}
- pPrivate = get_sam3_bank_private(bank);
- if (!(pPrivate->probed))
+ private = get_sam3_bank_private(bank);
+ if (!(private->probed))
return ERROR_FLASH_BANK_NOT_PROBED;
- if ((first == 0) && ((last + 1) == pPrivate->nsectors)) {
+ if ((first == 0) && ((last + 1) == private->nsectors)) {
/* whole chip */
LOG_DEBUG("Here");
- return FLASHD_EraseEntireBank(pPrivate);
+ return flashd_erase_entire_bank(private);
}
LOG_INFO("sam3 auto-erases while programming (request ignored)");
return ERROR_OK;
static int sam3_protect(struct flash_bank *bank, int set, unsigned int first,
unsigned int last)
{
- struct sam3_bank_private *pPrivate;
+ struct sam3_bank_private *private;
int r;
LOG_DEBUG("Here");
return ERROR_TARGET_NOT_HALTED;
}
- pPrivate = get_sam3_bank_private(bank);
- if (!(pPrivate->probed))
+ private = get_sam3_bank_private(bank);
+ if (!(private->probed))
return ERROR_FLASH_BANK_NOT_PROBED;
if (set)
- r = FLASHD_Lock(pPrivate, first, last);
+ r = flashd_lock(private, first, last);
else
- r = FLASHD_Unlock(pPrivate, first, last);
+ r = flashd_unlock(private, first, last);
LOG_DEBUG("End: r=%d", r);
return r;
}
-static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
+static int sam3_page_read(struct sam3_bank_private *private, unsigned pagenum, uint8_t *buf)
{
uint32_t adr;
int r;
- adr = pagenum * pPrivate->page_size;
- adr += pPrivate->base_address;
+ adr = pagenum * private->page_size;
+ adr += private->base_address;
- r = target_read_memory(pPrivate->pChip->target,
+ r = target_read_memory(private->chip->target,
adr,
4, /* THIS*MUST*BE* in 32bit values */
- pPrivate->page_size / 4,
+ private->page_size / 4,
buf);
if (r != ERROR_OK)
LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
return r;
}
-static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
+static int sam3_page_write(struct sam3_bank_private *private, unsigned pagenum, const uint8_t *buf)
{
uint32_t adr;
uint32_t status;
uint32_t fmr; /* EEFC Flash Mode Register */
int r;
- adr = pagenum * pPrivate->page_size;
- adr += pPrivate->base_address;
+ adr = pagenum * private->page_size;
+ adr += private->base_address;
/* Get flash mode register value */
- r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
+ r = target_read_u32(private->chip->target, private->controller_address, &fmr);
if (r != ERROR_OK)
LOG_DEBUG("Error Read failed: read flash mode register");
fmr &= 0xfffff0ff;
/* set FWS (flash wait states) field in the FMR (flash mode register) */
- fmr |= (pPrivate->flash_wait_states << 8);
+ fmr |= (private->flash_wait_states << 8);
LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
- r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
+ r = target_write_u32(private->bank->target, private->controller_address, fmr);
if (r != ERROR_OK)
LOG_DEBUG("Error Write failed: set flash mode register");
LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
- r = target_write_memory(pPrivate->pChip->target,
+ r = target_write_memory(private->chip->target,
adr,
4, /* THIS*MUST*BE* in 32bit values */
- pPrivate->page_size / 4,
+ private->page_size / 4,
buf);
if (r != ERROR_OK) {
LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
return r;
}
- r = EFC_PerformCommand(pPrivate,
+ r = efc_perform_command(private,
/* send Erase & Write Page */
AT91C_EFC_FCMD_EWP,
pagenum,
unsigned page_end;
int r;
unsigned page_offset;
- struct sam3_bank_private *pPrivate;
+ struct sam3_bank_private *private;
uint8_t *pagebuffer;
/* in case we bail further below, set this to null */
goto done;
}
- pPrivate = get_sam3_bank_private(bank);
- if (!(pPrivate->probed)) {
+ private = get_sam3_bank_private(bank);
+ if (!(private->probed)) {
r = ERROR_FLASH_BANK_NOT_PROBED;
goto done;
}
- if ((offset + count) > pPrivate->size_bytes) {
+ if ((offset + count) > private->size_bytes) {
LOG_ERROR("Flash write error - past end of bank");
LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
(unsigned int)(offset),
(unsigned int)(count),
- (unsigned int)(pPrivate->size_bytes));
+ (unsigned int)(private->size_bytes));
r = ERROR_FAIL;
goto done;
}
- pagebuffer = malloc(pPrivate->page_size);
+ pagebuffer = malloc(private->page_size);
if (!pagebuffer) {
- LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
+ LOG_ERROR("No memory for %d Byte page buffer", (int)(private->page_size));
r = ERROR_FAIL;
goto done;
}
/* what page do we start & end in? */
- page_cur = offset / pPrivate->page_size;
- page_end = (offset + count - 1) / pPrivate->page_size;
+ page_cur = offset / private->page_size;
+ page_end = (offset + count - 1) / private->page_size;
LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
/* Handle special case - all one page. */
if (page_cur == page_end) {
LOG_DEBUG("Special case, all in one page");
- r = sam3_page_read(pPrivate, page_cur, pagebuffer);
+ r = sam3_page_read(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
- page_offset = (offset & (pPrivate->page_size-1));
+ page_offset = (offset & (private->page_size-1));
memcpy(pagebuffer + page_offset,
buffer,
count);
- r = sam3_page_write(pPrivate, page_cur, pagebuffer);
+ r = sam3_page_write(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
r = ERROR_OK;
}
/* non-aligned start */
- page_offset = offset & (pPrivate->page_size - 1);
+ page_offset = offset & (private->page_size - 1);
if (page_offset) {
LOG_DEBUG("Not-Aligned start");
/* read the partial */
- r = sam3_page_read(pPrivate, page_cur, pagebuffer);
+ r = sam3_page_read(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
/* over-write with new data */
- n = (pPrivate->page_size - page_offset);
+ n = (private->page_size - page_offset);
memcpy(pagebuffer + page_offset,
buffer,
n);
- r = sam3_page_write(pPrivate, page_cur, pagebuffer);
+ r = sam3_page_write(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
/* By checking that offset is correct here, we also
fix a clang warning */
- assert(offset % pPrivate->page_size == 0);
+ assert(offset % private->page_size == 0);
/* intermediate large pages */
/* also - the final *terminal* */
(int)page_cur, (int)page_end, (unsigned int)(count));
while ((page_cur < page_end) &&
- (count >= pPrivate->page_size)) {
- r = sam3_page_write(pPrivate, page_cur, buffer);
+ (count >= private->page_size)) {
+ r = sam3_page_write(private, page_cur, buffer);
if (r != ERROR_OK)
goto done;
- count -= pPrivate->page_size;
- buffer += pPrivate->page_size;
+ count -= private->page_size;
+ buffer += private->page_size;
page_cur += 1;
}
if (count) {
LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
/* we have a partial page */
- r = sam3_page_read(pPrivate, page_cur, pagebuffer);
+ r = sam3_page_read(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
/* data goes at start */
memcpy(pagebuffer, buffer, count);
- r = sam3_page_write(pPrivate, page_cur, pagebuffer);
+ r = sam3_page_write(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
}
COMMAND_HANDLER(sam3_handle_info_command)
{
- struct sam3_chip *pChip;
- pChip = get_current_sam3(CMD);
- if (!pChip)
+ struct sam3_chip *chip;
+ chip = get_current_sam3(CMD);
+ if (!chip)
return ERROR_OK;
unsigned x;
int r;
/* bank0 must exist before we can do anything */
- if (pChip->details.bank[0].pBank == NULL) {
+ if (chip->details.bank[0].bank == NULL) {
x = 0;
need_define:
command_print(CMD,
}
/* if bank 0 is not probed, then probe it */
- if (!(pChip->details.bank[0].probed)) {
- r = sam3_auto_probe(pChip->details.bank[0].pBank);
+ if (!(chip->details.bank[0].probed)) {
+ r = sam3_auto_probe(chip->details.bank[0].bank);
if (r != ERROR_OK)
return ERROR_FAIL;
}
/* auto-probe other banks, 0 done above */
for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
/* skip banks not present */
- if (!(pChip->details.bank[x].present))
+ if (!(chip->details.bank[x].present))
continue;
- if (pChip->details.bank[x].pBank == NULL)
+ if (chip->details.bank[x].bank == NULL)
goto need_define;
- if (pChip->details.bank[x].probed)
+ if (chip->details.bank[x].probed)
continue;
- r = sam3_auto_probe(pChip->details.bank[x].pBank);
+ r = sam3_auto_probe(chip->details.bank[x].bank);
if (r != ERROR_OK)
return r;
}
- r = sam3_GetInfo(pChip);
+ r = sam3_get_info(chip);
if (r != ERROR_OK) {
LOG_DEBUG("Sam3Info, Failed %d", r);
return r;
{
unsigned x, v;
int r, who;
- struct sam3_chip *pChip;
+ struct sam3_chip *chip;
- pChip = get_current_sam3(CMD);
- if (!pChip)
+ chip = get_current_sam3(CMD);
+ if (!chip)
return ERROR_OK;
- if (pChip->target->state != TARGET_HALTED) {
+ if (chip->target->state != TARGET_HALTED) {
LOG_ERROR("sam3 - target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- if (pChip->details.bank[0].pBank == NULL) {
+ if (chip->details.bank[0].bank == NULL) {
command_print(CMD, "Bank0 must be defined first via: flash bank %s ...",
at91sam3_flash.name);
return ERROR_FAIL;
}
- if (!pChip->details.bank[0].probed) {
- r = sam3_auto_probe(pChip->details.bank[0].pBank);
+ if (!chip->details.bank[0].probed) {
+ r = sam3_auto_probe(chip->details.bank[0].bank);
if (r != ERROR_OK)
return r;
}
if (who == -1) {
showall:
r = ERROR_OK;
- for (x = 0; x < pChip->details.n_gpnvms; x++) {
- r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
+ for (x = 0; x < chip->details.n_gpnvms; x++) {
+ r = flashd_get_gpnvm(&(chip->details.bank[0]), x, &v);
if (r != ERROR_OK)
break;
command_print(CMD, "sam3-gpnvm%u: %u", x, v);
}
return r;
}
- if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
- r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
+ if ((who >= 0) && (((unsigned)(who)) < chip->details.n_gpnvms)) {
+ r = flashd_get_gpnvm(&(chip->details.bank[0]), who, &v);
if (r == ERROR_OK)
command_print(CMD, "sam3-gpnvm%u: %u", who, v);
return r;
}
if (0 == strcmp("set", CMD_ARGV[0]))
- r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
+ r = flashd_set_gpnvm(&(chip->details.bank[0]), who);
else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
(0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
- r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
+ r = flashd_clr_gpnvm(&(chip->details.bank[0]), who);
else {
command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
r = ERROR_COMMAND_SYNTAX_ERROR;
COMMAND_HANDLER(sam3_handle_slowclk_command)
{
- struct sam3_chip *pChip;
+ struct sam3_chip *chip;
- pChip = get_current_sam3(CMD);
- if (!pChip)
+ chip = get_current_sam3(CMD);
+ if (!chip)
return ERROR_OK;
switch (CMD_ARGC) {
command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v));
return ERROR_COMMAND_SYNTAX_ERROR;
}
- pChip->cfg.slow_freq = v;
+ chip->cfg.slow_freq = v;
break;
}
default:
return ERROR_COMMAND_SYNTAX_ERROR;
}
command_print(CMD, "Slowclk freq: %d.%03dkhz",
- (int)(pChip->cfg.slow_freq / 1000),
- (int)(pChip->cfg.slow_freq % 1000));
+ (int)(chip->cfg.slow_freq / 1000),
+ (int)(chip->cfg.slow_freq % 1000));
return ERROR_OK;
}
projects / fw / openocd / blobdiff