+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2009 by Alexei Babich *
* Rezonans plc., Chelyabinsk, Russia *
* *
* Copyright (C) 2011 by Erik Ahlen *
* Avalon Innovation, Sweden *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
/*
static const char target_not_halted_err_msg[] =
"target must be halted to use mxc NAND flash controller";
static const char data_block_size_err_msg[] =
- "minimal granularity is one half-word, %" PRId32 " is incorrect";
+ "minimal granularity is one half-word, %" PRIu32 " is incorrect";
static const char sram_buffer_bounds_err_msg[] =
"trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
static const char get_status_register_err_msg[] = "can't get NAND status";
int hwecc_needed;
mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
- if (mxc_nf_info == NULL) {
+ if (!mxc_nf_info) {
LOG_ERROR("no memory for nand controller");
return ERROR_FAIL;
}
(nand->target->endianness == TARGET_LITTLE_ENDIAN);
/*
- * should factory bad block indicator be swaped
+ * should factory bad block indicator be swapped
* as a workaround for how the nfc handles pages.
*/
if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
if (retval != ERROR_OK) {
- command_print(CMD_CTX, "invalid nand device number or name: %s", CMD_ARGV[0]);
+ command_print(CMD, "invalid nand device number or name: %s", CMD_ARGV[0]);
return ERROR_COMMAND_ARGUMENT_INVALID;
}
mxc_nf_info->flags.biswap_enabled = false;
}
if (mxc_nf_info->flags.biswap_enabled)
- command_print(CMD_CTX, "BI-swapping enabled on %s", nand->name);
+ command_print(CMD, "BI-swapping enabled on %s", nand->name);
else
- command_print(CMD_CTX, "BI-swapping disabled on %s", nand->name);
+ command_print(CMD, "BI-swapping disabled on %s", nand->name);
return ERROR_OK;
}
static const struct command_registration mxc_sub_command_handlers[] = {
{
.name = "biswap",
+ .mode = COMMAND_EXEC,
.handler = handle_mxc_biswap_command,
- .help = "Turns on/off bad block information swaping from main area, "
+ .help = "Turns on/off bad block information swapping from main area, "
"without parameter query status.",
.usage = "bank_id ['enable'|'disable']",
},
.name = "mxc",
.mode = COMMAND_ANY,
.help = "MXC NAND flash controller commands",
- .chain = mxc_sub_command_handlers
+ .chain = mxc_sub_command_handlers,
+ .usage = "",
},
COMMAND_REGISTRATION_DONE
};
int validate_target_result;
uint16_t buffsize_register_content;
uint32_t sreg_content;
- uint32_t SREG = MX2_FMCR;
- uint32_t SEL_16BIT = MX2_FMCR_NF_16BIT_SEL;
- uint32_t SEL_FMS = MX2_FMCR_NF_FMS;
+ uint32_t sreg = MX2_FMCR;
+ uint32_t sel_16bit = MX2_FMCR_NF_16BIT_SEL;
+ uint32_t sel_fms = MX2_FMCR_NF_FMS;
int retval;
uint16_t nand_status_content;
/*
mxc_nf_info->flags.one_kb_sram = 0;
if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) {
- SREG = MX3_PCSR;
- SEL_16BIT = MX3_PCSR_NF_16BIT_SEL;
- SEL_FMS = MX3_PCSR_NF_FMS;
+ sreg = MX3_PCSR;
+ sel_16bit = MX3_PCSR_NF_16BIT_SEL;
+ sel_fms = MX3_PCSR_NF_FMS;
} else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) {
- SREG = MX25_RCSR;
- SEL_16BIT = MX25_RCSR_NF_16BIT_SEL;
- SEL_FMS = MX25_RCSR_NF_FMS;
+ sreg = MX25_RCSR;
+ sel_16bit = MX25_RCSR_NF_16BIT_SEL;
+ sel_fms = MX25_RCSR_NF_FMS;
} else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
- SREG = MX35_RCSR;
- SEL_16BIT = MX35_RCSR_NF_16BIT_SEL;
- SEL_FMS = MX35_RCSR_NF_FMS;
+ sreg = MX35_RCSR;
+ sel_16bit = MX35_RCSR_NF_16BIT_SEL;
+ sel_fms = MX35_RCSR_NF_FMS;
}
- target_read_u32(target, SREG, &sreg_content);
+ target_read_u32(target, sreg, &sreg_content);
if (!nand->bus_width) {
/* bus_width not yet defined. Read it from MXC_FMCR */
- nand->bus_width = (sreg_content & SEL_16BIT) ? 16 : 8;
+ nand->bus_width = (sreg_content & sel_16bit) ? 16 : 8;
} else {
/* bus_width forced in soft. Sync it to MXC_FMCR */
- sreg_content |= ((nand->bus_width == 16) ? SEL_16BIT : 0x00000000);
- target_write_u32(target, SREG, sreg_content);
+ sreg_content |= ((nand->bus_width == 16) ? sel_16bit : 0x00000000);
+ target_write_u32(target, sreg, sreg_content);
}
if (nand->bus_width == 16)
LOG_DEBUG("MXC_NF : bus is 16-bit width");
LOG_DEBUG("MXC_NF : bus is 8-bit width");
if (!nand->page_size)
- nand->page_size = (sreg_content & SEL_FMS) ? 2048 : 512;
+ nand->page_size = (sreg_content & sel_fms) ? 2048 : 512;
else {
- sreg_content |= ((nand->page_size == 2048) ? SEL_FMS : 0x00000000);
- target_write_u32(target, SREG, sreg_content);
+ sreg_content |= ((nand->page_size == 2048) ? sel_fms : 0x00000000);
+ target_write_u32(target, sreg, sreg_content);
}
if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
LOG_ERROR("NAND controller have only 1 kb SRAM, so "
mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
break;
default:
- /* Ohter command use the default 'One page data out' FDO */
+ /* Other command use the default 'One page data out' FDO */
mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
break;
}
if (oob) {
if (mxc_nf_info->flags.hw_ecc_enabled) {
/*
- * part of spare block will be overrided by hardware
+ * part of spare block will be overridden by hardware
* ECC generator
*/
- LOG_DEBUG("part of spare block will be overrided "
+ LOG_DEBUG("part of spare block will be overridden "
"by hardware ECC generator");
}
if (nfc_is_v1())
}
if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
- uint32_t SPARE_BUFFER3;
+ uint32_t spare_buffer3;
/* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
if (nfc_is_v1())
- SPARE_BUFFER3 = MXC_NF_V1_SPARE_BUFFER3 + 4;
+ spare_buffer3 = MXC_NF_V1_SPARE_BUFFER3 + 4;
else
- SPARE_BUFFER3 = MXC_NF_V2_SPARE_BUFFER3;
- target_read_u16(target, SPARE_BUFFER3, &swap2);
+ spare_buffer3 = MXC_NF_V2_SPARE_BUFFER3;
+ target_read_u16(target, spare_buffer3, &swap2);
new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
swap2 = (swap1 << 8) | (swap2 & 0xFF);
target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
- target_write_u16(target, SPARE_BUFFER3, swap2);
+ target_write_u16(target, spare_buffer3, swap2);
}
if (data)
uint16_t work_mode = 0;
uint16_t temp;
/*
- * resets NAND flash controller in zero time ? I dont know.
+ * resets NAND flash controller in zero time ? I don't know.
*/
target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
return ERROR_OK;
}
-int ecc_status_v1(struct nand_device *nand)
+static int ecc_status_v1(struct nand_device *nand)
{
struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
struct target *target = nand->target;
case 2 << 2:
LOG_INFO("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
- break;
}
switch (ecc_status & 0x0003) {
case 1:
case 2:
LOG_INFO("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
- break;
}
return ERROR_OK;
}
-int ecc_status_v2(struct nand_device *nand)
+static int ecc_status_v2(struct nand_device *nand)
{
struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
struct target *target = nand->target;
projects / fw / openocd / blobdiff