* read/write data to the SLC controller.
* - DMA descriptors will be put at start of working area,
* - Hardware generated ECC will be stored at ECC_OFFS
- * - OOB wil be read/written from/to SPARE_OFFS
+ * - OOB will be read/written from/to SPARE_OFFS
* - Actual page data will be read from/to DATA_OFFS
* There are unused holes between the used areas.
*/
58, 59, 60, 61, 62, 63
};
-typedef struct {
+struct dmac_ll {
volatile uint32_t dma_src;
volatile uint32_t dma_dest;
volatile uint32_t next_lli;
volatile uint32_t next_ctrl;
-} dmac_ll_t;
+};
-static dmac_ll_t dmalist[(2048/256) * 2 + 1];
+static struct dmac_ll dmalist[(2048/256) * 2 + 1];
/* nand device lpc32xx <target#> <oscillator_frequency>
*/
"1000 and 20000 kHz, was %i",
lpc32xx_info->osc_freq);
- lpc32xx_info->selected_controller = LPC32xx_NO_CONTROLLER;
+ lpc32xx_info->selected_controller = LPC32XX_NO_CONTROLLER;
lpc32xx_info->sw_write_protection = 0;
lpc32xx_info->sw_wp_lower_bound = 0x0;
lpc32xx_info->sw_wp_upper_bound = 0x0;
/* determine current SYSCLK (13'MHz or main oscillator) */
retval = target_read_u32(target, 0x40004050, &sysclk_ctrl);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read SYSCLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
/* determine selected HCLK source */
retval = target_read_u32(target, 0x40004044, &pwr_ctrl);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read HCLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
hclk = sysclk;
else {
retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read HCLKPLL_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
hclk_pll = lpc32xx_pll(sysclk, hclkpll_ctrl);
retval = target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read CLKDIV_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
{
struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
struct target *target = nand->target;
- int bus_width = nand->bus_width ? : 8;
- int address_cycles = nand->address_cycles ? : 3;
- int page_size = nand->page_size ? : 512;
+ int bus_width = nand->bus_width ? nand->bus_width : 8;
+ int address_cycles = nand->address_cycles ? nand->address_cycles : 3;
+ int page_size = nand->page_size ? nand->page_size : 512;
int retval;
if (target->state != TARGET_HALTED) {
}
/* select MLC controller if none is currently selected */
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_DEBUG("no LPC32xx NAND flash controller selected, "
"using default 'slc'");
- lpc32xx_info->selected_controller = LPC32xx_SLC_CONTROLLER;
+ lpc32xx_info->selected_controller = LPC32XX_SLC_CONTROLLER;
}
- if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint32_t mlc_icr_value = 0x0;
float cycle;
int twp, twh, trp, treh, trhz, trbwb, tcea;
/* FLASHCLK_CTRL = 0x22 (enable clk for MLC) */
retval = target_write_u32(target, 0x400040c8, 0x22);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set FLASHCLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_CEH = 0x0 (Force nCE assert) */
retval = target_write_u32(target, 0x200b804c, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CEH");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_LOCK = 0xa25e (unlock protected registers) */
retval = target_write_u32(target, 0x200b8044, 0xa25e);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_LOCK");
return ERROR_NAND_OPERATION_FAILED;
}
if (bus_width == 16)
mlc_icr_value |= 0x1;
retval = target_write_u32(target, 0x200b8030, mlc_icr_value);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ICR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_LOCK = 0xa25e (unlock protected registers) */
retval = target_write_u32(target, 0x200b8044, 0xa25e);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_LOCK");
return ERROR_NAND_OPERATION_FAILED;
}
| ((trhz & 0x7) << 16)
| ((trbwb & 0x1f) << 19)
| ((tcea & 0x3) << 24));
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_TIME_REG");
return ERROR_NAND_OPERATION_FAILED;
}
retval = lpc32xx_reset(nand);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
float cycle;
int r_setup, r_hold, r_width, r_rdy;
int w_setup, w_hold, w_width, w_rdy;
/* FLASHCLK_CTRL = 0x05 (enable clk for SLC) */
retval = target_write_u32(target, 0x400040c8, 0x05);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set FLASHCLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
/* after reset set other registers of SLC,
- * so reset calling is here at the begining
+ * so reset calling is here at the beginning
*/
retval = lpc32xx_reset(nand);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return ERROR_NAND_OPERATION_FAILED;
/* SLC_CFG =
*/
retval = target_write_u32(target, 0x20020014,
0x3e | ((bus_width == 16) ? 1 : 0));
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_CFG");
return ERROR_NAND_OPERATION_FAILED;
}
/* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
retval = target_write_u32(target, 0x20020020, 0x03);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_IEN");
return ERROR_NAND_OPERATION_FAILED;
}
/* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
retval = target_write_u32(target, 0x400040e8, 0x01);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set DMACLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
/* DMACConfig = DMA enabled*/
retval = target_write_u32(target, 0x31000030, 0x01);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set DMACConfig");
return ERROR_NAND_OPERATION_FAILED;
}
| ((w_hold & 0xf) << 20)
| ((w_width & 0xf) << 24)
| ((w_rdy & 0xf) << 28));
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_TAC");
return ERROR_NAND_OPERATION_FAILED;
}
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = 0xff (reset controller and NAND device) */
retval = target_write_u32(target, 0x200b8000, 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
"after reset");
return ERROR_NAND_OPERATION_TIMEOUT;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
retval = target_write_u32(target, 0x20020010, 0x6);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = command */
retval = target_write_u32(target, 0x200b8000, command);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CMD = command */
retval = target_write_u32(target, 0x20020008, command);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_ADDR = address */
retval = target_write_u32(target, 0x200b8004, address);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_ADDR = address */
retval = target_write_u32(target, 0x20020004, address);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_DATA = data */
retval = target_write_u32(target, 0x200b0000, data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_DATA = data */
retval = target_write_u32(target, 0x20020000, data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* data = MLC_DATA, use sized access */
if (nand->bus_width == 8) {
uint8_t *data8 = data;
LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
return ERROR_NAND_OPERATION_FAILED;
}
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t data32;
/* data = SLC_DATA, must use 32-bit access */
retval = target_read_u32(target, 0x20020000, &data32);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read SLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_CMD = sequential input */
retval = target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
if (nand->page_size == 512) {
/* MLC_ADDR = 0x0 (one column cycle) */
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_ADDR = row */
retval = target_write_u32(target, 0x200b8004, page & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
(page >> 8) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
if (nand->address_cycles == 4) {
retval = target_write_u32(target, 0x200b8004,
(page >> 16) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
} else {
/* MLC_ADDR = 0x0 (two column cycles) */
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_ADDR = row */
retval = target_write_u32(target, 0x200b8004, page & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
(page >> 8) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* write MLC_ECC_ENC_REG to start encode cycle */
retval = target_write_u32(target, 0x200b8008, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ECC_ENC_REG");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_memory(target, 0x200a8000,
4, 128, page_buffer);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_BUF (data)");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_memory(target, 0x200a8000,
1, 6, oob_buffer);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_BUF (oob)");
return ERROR_NAND_OPERATION_FAILED;
}
/* write MLC_ECC_AUTO_ENC_REG to start auto encode */
retval = target_write_u32(target, 0x200b8010, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ECC_AUTO_ENC_REG");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_CMD = auto program command */
retval = target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
* 2. Copy generated ECC data from Register to Spare Area
* 3. X'fer next 256 bytes of data from Memory to Flash.
* 4. Copy generated ECC data from Register to Spare Area.
- * 5. X'fer 16 byets of Spare area from Memory to Flash.
+ * 5. X'fer 16 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Small Block NAND
* ----------------------------------------------------------
* 1. X'fer 256 bytes of data from Flash to Memory.
* 5. X'fer 16 bytes of Spare area from Flash to Memory.
* Write Operation Sequence for Large Block NAND
* ----------------------------------------------------------
- * 1. Steps(1-4) of Write Operations repeate for four times
+ * 1. Steps(1-4) of Write Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Large Block NAND
* ----------------------------------------------------------
- * 1. Steps(1-4) of Read Operations repeate for four times
+ * 1. Steps(1-4) of Read Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Flash to Memory.
* 2. Copy generated ECC data from Register to Spare Area
* 3. X'fer next 256 bytes of data from Memory to Flash.
* 4. Copy generated ECC data from Register to Spare Area.
- * 5. X'fer 16 byets of Spare area from Memory to Flash.
+ * 5. X'fer 16 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Small Block NAND
* ----------------------------------------------------------
* 1. X'fer 256 bytes of data from Flash to Memory.
* 5. X'fer 16 bytes of Spare area from Flash to Memory.
* Write Operation Sequence for Large Block NAND
* ----------------------------------------------------------
- * 1. Steps(1-4) of Write Operations repeate for four times
+ * 1. Steps(1-4) of Write Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Large Block NAND
* ----------------------------------------------------------
- * 1. Steps(1-4) of Read Operations repeate for four times
+ * 1. Steps(1-4) of Read Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Flash to Memory.
dmalist[i*2].dma_src = (do_read ? dmasrc : (dmasrc + i * 256));
dmalist[i*2].dma_dest = (do_read ? (dmadst + i * 256) : dmadst);
dmalist[i*2].next_lli =
- target_mem_base + (i*2 + 1) * sizeof(dmac_ll_t);
+ target_mem_base + (i*2 + 1) * sizeof(struct dmac_ll);
dmalist[i*2].next_ctrl = ctrl;
dmalist[(i*2) + 1].dma_src = 0x20020034;/* SLC_ECC */
dmalist[(i*2) + 1].dma_dest =
target_mem_base + ECC_OFFS + i * 4;
dmalist[(i*2) + 1].next_lli =
- target_mem_base + (i*2 + 2) * sizeof(dmac_ll_t);
+ target_mem_base + (i*2 + 2) * sizeof(struct dmac_ll);
dmalist[(i*2) + 1].next_ctrl = ecc_ctrl;
}
/* DMACIntTCClear = ch0 */
retval = target_write_u32(target, 0x31000008, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACIntTCClear");
return retval;
}
/* DMACIntErrClear = ch0 */
retval = target_write_u32(target, 0x31000010, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACIntErrClear");
return retval;
}
retval = target_write_u32(target, 0x31000110,
1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
| 0<<15 | 0<<16 | 0<<18);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACC0Config");
return retval;
}
/* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
retval = target_write_u32(target, 0x20020010, 0x3);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set SLC_CTRL");
return retval;
}
/* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
retval = target_write_u32(target, 0x20020028, 2);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set SLC_ICR");
return retval;
}
/* SLC_TC */
retval = target_write_u32(target, 0x20020030, count);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("lpc32xx_start_slc_dma: Could not set SLC_TC");
return retval;
}
/* Read DMACRawIntTCStat */
retval = target_read_u32(target, 0x31000014, &tc_stat);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read DMACRawIntTCStat");
return 0;
}
/* Read DMACRawIntErrStat */
retval = target_read_u32(target, 0x31000018, &err_stat);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read DMACRawIntErrStat");
return 0;
}
target_mem_base = pworking_area->address;
/*
- * Skip writting page which has all 0xFF data as this will
+ * Skip writing page which has all 0xFF data as this will
* generate 0x0 value.
*/
if (data && !oob) {
XXX: Assumes host and target have same byte sex.
*/
retval = target_write_memory(target, target_mem_base, 4,
- nll * sizeof(dmac_ll_t) / 4,
+ nll * sizeof(struct dmac_ll) / 4,
(uint8_t *)dmalist);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write DMA descriptors to IRAM");
return retval;
}
retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("NAND_CMD_SEQIN failed");
return retval;
}
WIDTH = bus_width
*/
retval = target_write_u32(target, 0x20020014, 0x3c);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set SLC_CFG");
return retval;
}
retval = target_write_memory(target,
target_mem_base + DATA_OFFS,
4, nand->page_size/4, fdata);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write data to IRAM");
return retval;
}
- /* Write first decriptor to DMA controller */
+ /* Write first descriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
- sizeof(dmac_ll_t) / 4,
+ sizeof(struct dmac_ll) / 4,
(uint8_t *)dmalist);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write DMA descriptor to DMAC");
return retval;
}
int tot_size = nand->page_size;
tot_size += tot_size == 2048 ? 64 : 16;
retval = lpc32xx_start_slc_dma(nand, tot_size, 0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("DMA failed");
return retval;
}
static uint32_t hw_ecc[8];
retval = target_read_memory(target, target_mem_base + ECC_OFFS,
4, ecc_count, (uint8_t *)hw_ecc);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Reading hw generated ECC from IRAM failed");
return retval;
}
}
retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4,
foob_size / 4, foob);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Writing OOB to IRAM failed");
return retval;
}
- /* Write OOB decriptor to DMA controller */
+ /* Write OOB descriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
- sizeof(dmac_ll_t) / 4,
+ sizeof(struct dmac_ll) / 4,
(uint8_t *)(&dmalist[nll-1]));
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write OOB DMA descriptor to DMAC");
return retval;
}
/* DMACIntTCClear = ch0 */
retval = target_write_u32(target, 0x31000008, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACIntTCClear");
return retval;
}
retval = target_write_u32(target, 0x31000110,
1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
| 0<<15 | 0<<16 | 0<<18);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACC0Config");
return retval;
}
} else {
/* Start xfer of data from iram to flash using DMA */
retval = lpc32xx_start_slc_dma(nand, foob_size, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("DMA OOB failed");
return retval;
}
/* Let NAND start actual writing */
retval = nand_write_finish(nand);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("nand_write_finish failed");
return retval;
}
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
if (!data && oob) {
LOG_ERROR("LPC32xx MLC controller can't write "
"OOB data only");
retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
oob, oob_size);
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
struct working_area *pworking_area;
if (!data && oob) {
/*
/* MLC_CMD = Read0 */
retval = target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
}
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
/* small page device
* MLC_ADDR = 0x0 (one column cycle) */
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_ADDR = row */
retval = target_write_u32(target, 0x200b8004, page & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
(page >> 8) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
if (nand->address_cycles == 4) {
retval = target_write_u32(target, 0x200b8004,
(page >> 16) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* large page device
* MLC_ADDR = 0x0 (two column cycles) */
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_ADDR = row */
retval = target_write_u32(target, 0x200b8004, page & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
(page >> 8) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_CMD = Read Start */
retval = target_write_u32(target, 0x200b8000,
NAND_CMD_READSTART);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
while (page_bytes_done < (uint32_t)nand->page_size) {
/* MLC_ECC_AUTO_DEC_REG = dummy */
retval = target_write_u32(target, 0x200b8014, 0xaa55aa55);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ECC_AUTO_DEC_REG");
return ERROR_NAND_OPERATION_FAILED;
}
}
retval = target_read_u32(target, 0x200b8048, &mlc_isr);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read MLC_ISR");
return ERROR_NAND_OPERATION_FAILED;
}
if (data) {
retval = target_read_memory(target, 0x200a8000, 4, 128,
page_buffer + page_bytes_done);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read MLC_BUF (data)");
return ERROR_NAND_OPERATION_FAILED;
}
if (oob) {
retval = target_read_memory(target, 0x200a8000, 4, 4,
oob_buffer + oob_bytes_done);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read MLC_BUF (oob)");
return ERROR_NAND_OPERATION_FAILED;
}
XXX: Assumes host and target have same byte sex.
*/
retval = target_write_memory(target, target_mem_base, 4,
- nll * sizeof(dmac_ll_t) / 4,
+ nll * sizeof(struct dmac_ll) / 4,
(uint8_t *)dmalist);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write DMA descriptors to IRAM");
return retval;
}
retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("lpc32xx_read_page_slc: NAND_CMD_READ0 failed");
return retval;
}
WIDTH = bus_width
*/
retval = target_write_u32(target, 0x20020014, 0x3e);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("lpc32xx_read_page_slc: Could not set SLC_CFG");
return retval;
}
- /* Write first decriptor to DMA controller */
+ /* Write first descriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
- sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist);
- if (ERROR_OK != retval) {
+ sizeof(struct dmac_ll) / 4, (uint8_t *)dmalist);
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write DMA descriptor to DMAC");
return retval;
}
int tot_size = nand->page_size;
tot_size += nand->page_size == 2048 ? 64 : 16;
retval = lpc32xx_start_slc_dma(nand, tot_size, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("lpc32xx_read_page_slc: DMA read failed");
return retval;
}
if (data) {
retval = target_read_memory(target, target_mem_base + DATA_OFFS,
4, data_size/4, data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read data from IRAM");
return retval;
}
retval = target_read_memory(target,
target_mem_base + SPARE_OFFS, 4,
oob_size/4, oob);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read OOB from IRAM");
return retval;
}
retval = target_read_memory(target, target_mem_base + SPARE_OFFS,
4, nand->page_size == 2048 ? 16 : 4, foob);
lpc32xx_dump_oob(foob, nand->page_size == 2048 ? 64 : 16);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read OOB from IRAM");
return retval;
}
static uint32_t hw_ecc[8]; /* max size */
retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4,
ecc_count, (uint8_t *)hw_ecc);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read hw generated ECC from IRAM");
return retval;
}
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
if (data_size > (uint32_t)nand->page_size) {
LOG_ERROR("data size exceeds page size");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
oob, oob_size);
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
struct working_area *pworking_area;
retval = target_alloc_working_area(target,
LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);
do {
- if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint8_t status;
/* Read MLC_ISR, wait for controller to become ready */
retval = target_read_u8(target, 0x200b8048, &status);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_STAT");
return ERROR_NAND_OPERATION_FAILED;
}
timeout);
return 1;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t status;
/* Read SLC_STAT and check READY bit */
retval = target_read_u32(target, 0x20020018, &status);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_STAT");
return ERROR_NAND_OPERATION_FAILED;
}
LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);
do {
- if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint8_t status = 0x0;
/* Read MLC_ISR, wait for NAND flash device to
* become ready */
retval = target_read_u8(target, 0x200b8048, &status);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read MLC_ISR");
return ERROR_NAND_OPERATION_FAILED;
}
timeout);
return 1;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t status = 0x0;
/* Read SLC_STAT and check READY bit */
retval = target_read_u32(target, 0x20020018, &status);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read SLC_STAT");
return ERROR_NAND_OPERATION_FAILED;
}
int retval;
/* Read SLC_INT_STAT and check INT_TC_STAT bit */
retval = target_read_u32(target, 0x2002001c, &status);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read SLC_INT_STAT");
return 0;
}
if (CMD_ARGC >= 2) {
if (strcmp(CMD_ARGV[1], "mlc") == 0) {
lpc32xx_info->selected_controller =
- LPC32xx_MLC_CONTROLLER;
+ LPC32XX_MLC_CONTROLLER;
} else if (strcmp(CMD_ARGV[1], "slc") == 0) {
lpc32xx_info->selected_controller =
- LPC32xx_SLC_CONTROLLER;
+ LPC32XX_SLC_CONTROLLER;
} else
return ERROR_COMMAND_SYNTAX_ERROR;
}
projects / fw / openocd / blobdiff