+// SPDX-License-Identifier: GPL-2.0-or-later
+
/*
* Copyright (C) 2009 by Dean Glazeski
* dnglaze@gmail.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the
- * Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "imp.h"
#include "arm_io.h"
-#define AT91C_PIOx_SODR (0x30) /**< Offset to PIO SODR. */
-#define AT91C_PIOx_CODR (0x34) /**< Offset to PIO CODR. */
-#define AT91C_PIOx_PDSR (0x3C) /**< Offset to PIO PDSR. */
-#define AT91C_ECCx_CR (0x00) /**< Offset to ECC CR. */
-#define AT91C_ECCx_SR (0x08) /**< Offset to ECC SR. */
-#define AT91C_ECCx_PR (0x0C) /**< Offset to ECC PR. */
-#define AT91C_ECCx_NPR (0x10) /**< Offset to ECC NPR. */
+#define AT91C_PIOX_SODR (0x30) /**< Offset to PIO SODR. */
+#define AT91C_PIOX_CODR (0x34) /**< Offset to PIO CODR. */
+#define AT91C_PIOX_PDSR (0x3C) /**< Offset to PIO PDSR. */
+#define AT91C_ECCX_CR (0x00) /**< Offset to ECC CR. */
+#define AT91C_ECCX_SR (0x08) /**< Offset to ECC SR. */
+#define AT91C_ECCX_PR (0x0C) /**< Offset to ECC PR. */
+#define AT91C_ECCX_NPR (0x10) /**< Offset to ECC NPR. */
/**
* Representation of a pin on an AT91SAM9 chip.
{
struct target *target = nand->target;
- if (!at91sam9_halted(target, "init")) {
+ if (!at91sam9_halted(target, "init"))
return ERROR_NAND_OPERATION_FAILED;
- }
return ERROR_OK;
}
/**
* Enable NAND device attached to a controller.
*
- * @param info NAND controller information for controlling NAND device.
+ * @param nand NAND controller information for controlling NAND device.
* @return Success or failure of the enabling.
*/
static int at91sam9_enable(struct nand_device *nand)
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
- return target_write_u32(target, info->ce.pioc + AT91C_PIOx_CODR, 1 << info->ce.num);
+ return target_write_u32(target, info->ce.pioc + AT91C_PIOX_CODR, 1 << info->ce.num);
}
/**
* Disable NAND device attached to a controller.
*
- * @param info NAND controller information for controlling NAND device.
+ * @param nand NAND controller information for controlling NAND device.
* @return Success or failure of the disabling.
*/
static int at91sam9_disable(struct nand_device *nand)
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
- return target_write_u32(target, info->ce.pioc + AT91C_PIOx_SODR, 1 << info->ce.num);
+ return target_write_u32(target, info->ce.pioc + AT91C_PIOX_SODR, 1 << info->ce.num);
}
/**
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
- if (!at91sam9_halted(target, "command")) {
+ if (!at91sam9_halted(target, "command"))
return ERROR_NAND_OPERATION_FAILED;
- }
at91sam9_enable(nand);
*/
static int at91sam9_reset(struct nand_device *nand)
{
- if (!at91sam9_halted(nand->target, "reset")) {
+ if (!at91sam9_halted(nand->target, "reset"))
return ERROR_NAND_OPERATION_FAILED;
- }
return at91sam9_disable(nand);
}
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
- if (!at91sam9_halted(nand->target, "address")) {
+ if (!at91sam9_halted(nand->target, "address"))
return ERROR_NAND_OPERATION_FAILED;
- }
return target_write_u8(target, info->addr, address);
}
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
- if (!at91sam9_halted(nand->target, "read data")) {
+ if (!at91sam9_halted(nand->target, "read data"))
return ERROR_NAND_OPERATION_FAILED;
- }
return target_read_u8(target, info->data, data);
}
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
- if (!at91sam9_halted(target, "write data")) {
+ if (!at91sam9_halted(target, "write data"))
return ERROR_NAND_OPERATION_FAILED;
- }
return target_write_u8(target, info->data, data);
}
struct target *target = nand->target;
uint32_t status;
- if (!at91sam9_halted(target, "nand ready")) {
+ if (!at91sam9_halted(target, "nand ready"))
return 0;
- }
do {
- target_read_u32(target, info->busy.pioc + AT91C_PIOx_PDSR, &status);
+ target_read_u32(target, info->busy.pioc + AT91C_PIOX_PDSR, &status);
- if (status & (1 << info->busy.num)) {
+ if (status & (1 << info->busy.num))
return 1;
- }
alive_sleep(1);
} while (timeout-- > 0);
struct arm_nand_data *io = &info->io;
int status;
- if (!at91sam9_halted(nand->target, "read block")) {
+ if (!at91sam9_halted(nand->target, "read block"))
return ERROR_NAND_OPERATION_FAILED;
- }
io->chunk_size = nand->page_size;
status = arm_nandread(io, data, size);
struct arm_nand_data *io = &info->io;
int status;
- if (!at91sam9_halted(nand->target, "write block")) {
+ if (!at91sam9_halted(nand->target, "write block"))
return ERROR_NAND_OPERATION_FAILED;
- }
io->chunk_size = nand->page_size;
status = arm_nandwrite(io, data, size);
return ERROR_NAND_OPERATION_FAILED;
}
- // reset ECC parity registers
- return target_write_u32(target, info->ecc + AT91C_ECCx_CR, 1);
+ /* reset ECC parity registers */
+ return target_write_u32(target, info->ecc + AT91C_ECCX_CR, 1);
}
/**
* @param size Size of the OOB.
* @return Pointer to an area to store OOB data.
*/
-static uint8_t * at91sam9_oob_init(struct nand_device *nand, uint8_t *oob, uint32_t *size)
+static uint8_t *at91sam9_oob_init(struct nand_device *nand, uint8_t *oob, uint32_t *size)
{
if (!oob) {
- // user doesn't want OOB, allocate it
- if (nand->page_size == 512) {
+ /* user doesn't want OOB, allocate it */
+ if (nand->page_size == 512)
*size = 16;
- } else if (nand->page_size == 2048) {
+ else if (nand->page_size == 2048)
*size = 64;
- }
oob = malloc(*size);
if (!oob) {
LOG_ERROR("Unable to allocate space for OOB");
+ return NULL;
}
memset(oob, 0xFF, *size);
* @return Success or failure of reading the NAND page.
*/
static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
- uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
+ uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
int retval;
struct at91sam9_nand *info = nand->controller_priv;
uint32_t status;
retval = at91sam9_ecc_init(target, info);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK)
return retval;
- }
retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK)
return retval;
- }
if (data) {
retval = nand_read_data_page(nand, data, data_size);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK)
return retval;
- }
}
oob_data = at91sam9_oob_init(nand, oob, &oob_size);
retval = nand_read_data_page(nand, oob_data, oob_size);
- if (ERROR_OK == retval && data) {
- target_read_u32(target, info->ecc + AT91C_ECCx_SR, &status);
+ if (retval == ERROR_OK && data) {
+ target_read_u32(target, info->ecc + AT91C_ECCX_SR, &status);
if (status & 1) {
LOG_ERROR("Error detected!");
- if (status & 4) {
+ if (status & 4)
LOG_ERROR("Multiple errors encountered; unrecoverable!");
- } else {
- // attempt recovery
+ else {
+ /* attempt recovery */
uint32_t parity;
target_read_u32(target,
- info->ecc + AT91C_ECCx_PR,
- &parity);
+ info->ecc + AT91C_ECCX_PR,
+ &parity);
uint32_t word = (parity & 0x0000FFF0) >> 4;
uint32_t bit = parity & 0x0F;
data[word] ^= (0x1) << bit;
LOG_INFO("Data word %d, bit %d corrected.",
- (unsigned) word,
- (unsigned) bit);
+ (unsigned) word,
+ (unsigned) bit);
}
}
if (status & 2) {
- // we could write back correct ECC data
+ /* we could write back correct ECC data */
LOG_ERROR("Error in ECC bytes detected");
}
}
if (!oob) {
- // if it wasn't asked for, free it
+ /* if it wasn't asked for, free it */
free(oob_data);
}
* @return Success or failure of the page write.
*/
static int at91sam9_write_page(struct nand_device *nand, uint32_t page,
- uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
+ uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
uint32_t parity, nparity;
retval = at91sam9_ecc_init(target, info);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK)
return retval;
- }
retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK)
return retval;
- }
if (data) {
retval = nand_write_data_page(nand, data, data_size);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Unable to write data to NAND device");
return retval;
}
oob_data = at91sam9_oob_init(nand, oob, &oob_size);
if (!oob) {
- // no OOB given, so read in the ECC parity from the ECC controller
- target_read_u32(target, info->ecc + AT91C_ECCx_PR, &parity);
- target_read_u32(target, info->ecc + AT91C_ECCx_NPR, &nparity);
+ /* no OOB given, so read in the ECC parity from the ECC controller */
+ target_read_u32(target, info->ecc + AT91C_ECCX_PR, &parity);
+ target_read_u32(target, info->ecc + AT91C_ECCX_NPR, &nparity);
oob_data[0] = (uint8_t) parity;
oob_data[1] = (uint8_t) (parity >> 8);
retval = nand_write_data_page(nand, oob_data, oob_size);
- if (!oob) {
+ if (!oob)
free(oob_data);
- }
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Unable to write OOB data to NAND");
return retval;
}
unsigned num, address_line;
if (CMD_ARGC != 2) {
- command_print(CMD_CTX, "incorrect number of arguments for 'at91sam9 cle' command");
+ command_print(CMD, "incorrect number of arguments for 'at91sam9 cle' command");
return ERROR_OK;
}
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
nand = get_nand_device_by_num(num);
if (!nand) {
- command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
+ command_print(CMD, "invalid nand device number: %s", CMD_ARGV[0]);
return ERROR_OK;
}
struct at91sam9_nand *info = NULL;
unsigned num, address_line;
- if (CMD_ARGC != 2) {
+ if (CMD_ARGC != 2)
return ERROR_COMMAND_SYNTAX_ERROR;
- }
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
nand = get_nand_device_by_num(num);
if (!nand) {
- command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
+ command_print(CMD, "invalid nand device number: %s", CMD_ARGV[0]);
return ERROR_COMMAND_ARGUMENT_INVALID;
}
struct at91sam9_nand *info = NULL;
unsigned num, base_pioc, pin_num;
- if (CMD_ARGC != 3) {
+ if (CMD_ARGC != 3)
return ERROR_COMMAND_SYNTAX_ERROR;
- }
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
nand = get_nand_device_by_num(num);
if (!nand) {
- command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
+ command_print(CMD, "invalid nand device number: %s", CMD_ARGV[0]);
return ERROR_COMMAND_ARGUMENT_INVALID;
}
struct at91sam9_nand *info = NULL;
unsigned num, base_pioc, pin_num;
- if (CMD_ARGC != 3) {
+ if (CMD_ARGC != 3)
return ERROR_COMMAND_SYNTAX_ERROR;
- }
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
nand = get_nand_device_by_num(num);
if (!nand) {
- command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
+ command_print(CMD, "invalid nand device number: %s", CMD_ARGV[0]);
return ERROR_COMMAND_ARGUMENT_INVALID;
}
.name = "at91sam9",
.mode = COMMAND_ANY,
.help = "AT91SAM9 NAND flash controller commands",
+ .usage = "",
.chain = at91sam9_sub_command_handlers,
},
COMMAND_REGISTRATION_DONE
projects / fw / openocd / blobdiff