};
struct davinci_nand {
- target_t *target;
+ struct target *target;
uint8_t chipsel; /* chipselect 0..3 == CS2..CS5 */
uint8_t eccmode;
struct arm_nand_data io;
/* page i/o for the relevant flavor of hardware ECC */
- int (*read_page)(struct nand_device_s *nand, uint32_t page,
+ int (*read_page)(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
- int (*write_page)(struct nand_device_s *nand, uint32_t page,
+ int (*write_page)(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
};
#define NANDERRADDR 0xd0 /* 4-bit ECC err addr, 1st of 2 */
#define NANDERRVAL 0xd8 /* 4-bit ECC err value, 1st of 2 */
-static int halted(target_t *target, const char *label)
+static int halted(struct target *target, const char *label)
{
if (target->state == TARGET_HALTED)
return true;
return false;
}
-static int davinci_register_commands(struct command_context_s *cmd_ctx)
-{
- return ERROR_OK;
-}
-
-static int davinci_init(struct nand_device_s *nand)
+static int davinci_init(struct nand_device *nand)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
uint32_t nandfcr;
if (!halted(target, "init"))
return ERROR_OK;
}
-static int davinci_reset(struct nand_device_s *nand)
+static int davinci_reset(struct nand_device *nand)
{
return ERROR_OK;
}
-static int davinci_nand_ready(struct nand_device_s *nand, int timeout)
+static int davinci_nand_ready(struct nand_device *nand, int timeout)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
uint32_t nandfsr;
/* NOTE: return code is zero/error, else success; not ERROR_* */
return 0;
}
-static int davinci_command(struct nand_device_s *nand, uint8_t command)
+static int davinci_command(struct nand_device *nand, uint8_t command)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
if (!halted(target, "command"))
return ERROR_NAND_OPERATION_FAILED;
return ERROR_OK;
}
-static int davinci_address(struct nand_device_s *nand, uint8_t address)
+static int davinci_address(struct nand_device *nand, uint8_t address)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
if (!halted(target, "address"))
return ERROR_NAND_OPERATION_FAILED;
return ERROR_OK;
}
-static int davinci_write_data(struct nand_device_s *nand, uint16_t data)
+static int davinci_write_data(struct nand_device *nand, uint16_t data)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
if (!halted(target, "write_data"))
return ERROR_NAND_OPERATION_FAILED;
return ERROR_OK;
}
-static int davinci_read_data(struct nand_device_s *nand, void *data)
+static int davinci_read_data(struct nand_device *nand, void *data)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
if (!halted(target, "read_data"))
return ERROR_NAND_OPERATION_FAILED;
/* REVISIT a bit of native code should let block reads be MUCH faster */
-static int davinci_read_block_data(struct nand_device_s *nand,
+static int davinci_read_block_data(struct nand_device *nand,
uint8_t *data, int data_size)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
uint32_t nfdata = info->data;
uint32_t tmp;
return ERROR_OK;
}
-static int davinci_write_block_data(struct nand_device_s *nand,
+static int davinci_write_block_data(struct nand_device *nand,
uint8_t *data, int data_size)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
uint32_t nfdata = info->data;
uint32_t tmp;
int status;
return ERROR_OK;
}
-static int davinci_write_page(struct nand_device_s *nand, uint32_t page,
+static int davinci_write_page(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
struct davinci_nand *info = nand->controller_priv;
return status;
}
-static int davinci_read_page(struct nand_device_s *nand, uint32_t page,
+static int davinci_read_page(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
struct davinci_nand *info = nand->controller_priv;
return info->read_page(nand, page, data, data_size, oob, oob_size);
}
-static void davinci_write_pagecmd(struct nand_device_s *nand, uint8_t cmd, uint32_t page)
+static void davinci_write_pagecmd(struct nand_device *nand, uint8_t cmd, uint32_t page)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
int page3 = nand->address_cycles - (nand->page_size == 512);
/* write command ({page,otp}x{read,program} */
target_write_u8(target, info->addr, page >> 24);
}
-static int davinci_writepage_tail(struct nand_device_s *nand,
+static int davinci_writepage_tail(struct nand_device *nand,
uint8_t *oob, uint32_t oob_size)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
uint8_t status;
if (oob_size)
/*
* All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
*/
-static int davinci_write_page_ecc1(struct nand_device_s *nand, uint32_t page,
+static int davinci_write_page_ecc1(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
unsigned oob_offset;
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
const uint32_t fcr_addr = info->aemif + NANDFCR;
const uint32_t ecc1_addr = info->aemif + NANDFECC + (4 * info->chipsel);
uint32_t fcr, ecc1;
* is read first, so its ECC data can be used incrementally), but the
* manufacturer bad block markers are safe. Contrast: old "infix" style.
*/
-static int davinci_write_page_ecc4(struct nand_device_s *nand, uint32_t page,
+static int davinci_write_page_ecc4(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
static const uint8_t ecc512[] = {
struct davinci_nand *info = nand->controller_priv;
const uint8_t *l;
- target_t *target = info->target;
+ struct target *target = info->target;
const uint32_t fcr_addr = info->aemif + NANDFCR;
const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
uint32_t fcr, ecc4;
* older second stage loaders (ABL/U-Boot, etc) or other system software
* (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
*/
-static int davinci_write_page_ecc4infix(struct nand_device_s *nand, uint32_t page,
+static int davinci_write_page_ecc4infix(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
const uint32_t fcr_addr = info->aemif + NANDFCR;
const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
uint32_t fcr, ecc4;
return davinci_writepage_tail(nand, NULL, 0);
}
-static int davinci_read_page_ecc4infix(struct nand_device_s *nand, uint32_t page,
+static int davinci_read_page_ecc4infix(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
davinci_write_pagecmd(nand, NAND_CMD_READ0, page);
NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command)
{
struct davinci_nand *info;
- target_t *target;
+ struct target *target;
unsigned long chip, aemif;
enum ecc eccmode;
int chipsel;
* - aemif address
* Plus someday, optionally, ALE and CLE masks.
*/
- if (argc < 5) {
+ if (CMD_ARGC < 5) {
LOG_ERROR("parameters: %s target "
"chip_addr hwecc_mode aemif_addr",
- args[0]);
+ CMD_ARGV[0]);
goto fail;
}
- target = get_target(args[1]);
+ target = get_target(CMD_ARGV[1]);
if (!target) {
- LOG_ERROR("invalid target %s", args[1]);
+ LOG_ERROR("invalid target %s", CMD_ARGV[1]);
goto fail;
}
- COMMAND_PARSE_NUMBER(ulong, args[2], chip);
+ COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
if (chip == 0) {
- LOG_ERROR("Invalid NAND chip address %s", args[2]);
+ LOG_ERROR("Invalid NAND chip address %s", CMD_ARGV[2]);
goto fail;
}
- if (strcmp(args[3], "hwecc1") == 0)
+ if (strcmp(CMD_ARGV[3], "hwecc1") == 0)
eccmode = HWECC1;
- else if (strcmp(args[3], "hwecc4") == 0)
+ else if (strcmp(CMD_ARGV[3], "hwecc4") == 0)
eccmode = HWECC4;
- else if (strcmp(args[3], "hwecc4_infix") == 0)
+ else if (strcmp(CMD_ARGV[3], "hwecc4_infix") == 0)
eccmode = HWECC4_INFIX;
else {
- LOG_ERROR("Invalid ecc mode %s", args[3]);
+ LOG_ERROR("Invalid ecc mode %s", CMD_ARGV[3]);
goto fail;
}
- COMMAND_PARSE_NUMBER(ulong, args[4], aemif);
+ COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[4], aemif);
if (aemif == 0) {
- LOG_ERROR("Invalid AEMIF controller address %s", args[4]);
+ LOG_ERROR("Invalid AEMIF controller address %s", CMD_ARGV[4]);
goto fail;
}
struct nand_flash_controller davinci_nand_controller = {
.name = "davinci",
.nand_device_command = davinci_nand_device_command,
- .register_commands = davinci_register_commands,
.init = davinci_init,
.reset = davinci_reset,
.command = davinci_command,