{CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
{CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
{CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
+ {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL},
+ {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL},
+ {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL},
+ {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
{0, 0, NULL, NULL}
};
void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
{
- cfi_flash_bank_t *cfi_info = bank->driver_priv;
int i;
/* clear whole buffer, to ensure bits that exceed the bus_width
for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
cmd_buf[i] = 0;
- if (cfi_info->target->endianness == TARGET_LITTLE_ENDIAN)
+ if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
{
for (i = bank->bus_width; i > 0; i--)
{
*/
u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
{
- cfi_flash_bank_t *cfi_info = bank->driver_priv;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 data[CFI_MAX_BUS_WIDTH];
target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
- if (cfi_info->target->endianness == TARGET_LITTLE_ENDIAN)
+ if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
return data[0];
else
return data[bank->bus_width - 1];
*/
u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
{
- cfi_flash_bank_t *cfi_info = bank->driver_priv;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 data[CFI_MAX_BUS_WIDTH];
int i;
target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
- if (cfi_info->target->endianness == TARGET_LITTLE_ENDIAN)
+ if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
{
for (i = 0; i < bank->bus_width / bank->chip_width; i++)
data[0] |= data[i];
u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
{
- cfi_flash_bank_t *cfi_info = bank->driver_priv;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 data[CFI_MAX_BUS_WIDTH * 2];
target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
- if (cfi_info->target->endianness == TARGET_LITTLE_ENDIAN)
+ if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
return data[0] | data[bank->bus_width] << 8;
else
return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
{
- cfi_flash_bank_t *cfi_info = bank->driver_priv;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 data[CFI_MAX_BUS_WIDTH * 4];
target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
- if (cfi_info->target->endianness == TARGET_LITTLE_ENDIAN)
+ if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
else
return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
void cfi_intel_clear_status_register(flash_bank_t *bank)
{
- cfi_flash_bank_t *cfi_info = bank->driver_priv;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 command[8];
if (target->state != TARGET_HALTED)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 command[8];
cfi_info->pri_ext = pri_ext;
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 command[8];
cfi_info->pri_ext = pri_ext;
cfi_atmel_pri_ext_t atmel_pri_ext;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 command[8];
/* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
cfi_info->jedec_probe = 0;
cfi_info->not_cfi = 0;
- cfi_info->target = get_target_by_num(strtoul(args[5], NULL, 0));
- if (!cfi_info->target)
- {
- ERROR("no target '%s' configured", args[5]);
- exit(-1);
- }
-
for (i = 6; i < argc; i++)
{
if (strcmp(args[i], "x16_as_x8") == 0)
int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 command[8];
int i;
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 command[8];
int i;
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
- if (cfi_info->target->state != TARGET_HALTED)
+ if (bank->target->state != TARGET_HALTED)
{
return ERROR_TARGET_NOT_HALTED;
}
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 command[8];
int retry = 0;
int i;
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
- if (cfi_info->target->state != TARGET_HALTED)
+ if (bank->target->state != TARGET_HALTED)
{
return ERROR_TARGET_NOT_HALTED;
}
void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
{
- cfi_flash_bank_t *cfi_info = bank->driver_priv;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
int i;
int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
reg_param_t reg_params[7];
armv4_5_algorithm_t armv4_5_info;
working_area_t *source;
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
reg_param_t reg_params[10];
armv4_5_algorithm_t armv4_5_info;
working_area_t *source;
int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 command[8];
cfi_intel_clear_status_register(bank);
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 command[8];
cfi_command(bank, 0xaa, command);
int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u32 address = bank->base + offset; /* address of first byte to be programmed */
u32 write_p, copy_p;
int align; /* number of unaligned bytes */
int i;
int retval;
- if (cfi_info->target->state != TARGET_HALTED)
+ if (bank->target->state != TARGET_HALTED)
{
return ERROR_TARGET_NOT_HALTED;
}
int cfi_probe(struct flash_bank_s *bank)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 command[8];
int num_sectors = 0;
int i;
int cfi_erase_check(struct flash_bank_s *bank)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
int i;
int retval;
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 command[CFI_MAX_BUS_WIDTH];
int i;
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
- target_t *target = cfi_info->target;
+ target_t *target = bank->target;
u8 command[8];
int i;