SPEC_ADDR (sym->etype));
}
else {
- int size = getAllocSize (sym->type);
+ int size = getSize (sym->type) + sym->flexArrayLength;
if (size==0) {
werrorfl (sym->fileDef, sym->lineDef, E_UNKNOWN_SIZE, sym->name);
}
/* printIvalChar - generates initital value for character array */
/*-----------------------------------------------------------------*/
int
-printIvalChar (sym_link * type, initList * ilist, FILE * oFile, char *s)
+printIvalChar (symbol * sym, sym_link * type, initList * ilist, FILE * oFile, char *s)
{
value *val;
+ unsigned int size = DCL_ELEM (type);
if (!s)
{
-
val = list2val (ilist);
/* if the value is a character string */
if (IS_ARRAY (val->type) && IS_CHAR (val->etype))
{
- if (!DCL_ELEM (type))
- DCL_ELEM (type) = strlen (SPEC_CVAL (val->etype).v_char) + 1;
+ if (!size)
+ {
+ /* we have not been given a size, but now we know it */
+ size = strlen (SPEC_CVAL (val->etype).v_char) + 1;
+ /* but first check, if it's a flexible array */
+ if (sym && IS_STRUCT (sym->type))
+ sym->flexArrayLength = size;
+ else
+ DCL_ELEM (type) = size;
+ }
- printChar (oFile, SPEC_CVAL (val->etype).v_char, DCL_ELEM (type));
+ printChar (oFile, SPEC_CVAL (val->etype).v_char, size);
return 1;
}
werrorfl (ilist->filename, ilist->lineno, E_CONST_EXPECTED);
return;
}
- if (printIvalChar (type,
+ if (printIvalChar (sym, type,
(ilist->type == INIT_DEEP ? ilist->init.deep : ilist),
oFile, SPEC_CVAL (sym->etype).v_char))
return;
}
}
} else {
- // we have not been given a size, but we now know it
- DCL_ELEM (type) = size;
+ /* we have not been given a size, but now we know it */
+ /* but first check, if it's a flexible array */
+ if (IS_STRUCT (sym->type))
+ sym->flexArrayLength = size * getSize (type->next);
+ else
+ DCL_ELEM (type) = size;
}
return;
data, idata & bit & xdata */
emitRegularMap (data, TRUE, TRUE);
emitRegularMap (idata, TRUE, TRUE);
- emitRegularMap (bit, TRUE, FALSE);
+ emitRegularMap (bit, TRUE, TRUE);
emitRegularMap (pdata, TRUE, TRUE);
emitRegularMap (xdata, TRUE, TRUE);
if (port->genXINIT) {
emitRegularMap (home, TRUE, FALSE);
emitRegularMap (code, TRUE, FALSE);
+ if (options.const_seg) {
+ tfprintf (code->oFile, "\t!area\n", options.const_seg);
+ }
emitStaticSeg (statsg, code->oFile);
if (port->genXINIT) {
tfprintf (code->oFile, "\t!area\n", xinit->sname);
return;
}
- tfprintf (vFile, "\t!areacode\n", CODE_NAME);
+ tfprintf (vFile, "\t!areacode\n", HOME_NAME);
fprintf (vFile, "__interrupt_vect:\n");
--len;
for (p = dest, i = 0; *src != '\0' && i < len; ++src, ++i) {
- *p++ = isspace(*src) ? '_' : *src;
+ *p++ = isspace((unsigned char)*src) ? '_' : *src;
}
*p = '\0';
cdbStructBlock (0);
vFile = tempfile ();
- /* PENDING: this isnt the best place but it will do */
+ /* PENDING: this isn't the best place but it will do */
if (port->general.glue_up_main)
{
/* create the interrupt vector table */
{
/* copy the sbit segment */
fprintf (asmFile, "%s", iComments2);
- fprintf (asmFile, "; special function bits \n");
+ fprintf (asmFile, "; special function bits\n");
fprintf (asmFile, "%s", iComments2);
copyFile (asmFile, sfrbit->oFile);
if(RegBankUsed[0]||RegBankUsed[1]||RegBankUsed[2]||RegBankUsed[3])
{
fprintf (asmFile, "%s", iComments2);
- fprintf (asmFile, "; overlayable register banks \n");
+ fprintf (asmFile, "; overlayable register banks\n");
fprintf (asmFile, "%s", iComments2);
if(RegBankUsed[0])
- fprintf (asmFile, "\t.area REG_BANK_0\t(REL,OVR,DATA)\n\t.ds 8\n");
+ fprintf (asmFile, "\t.area REG_BANK_0\t(REL,OVR,DATA)\n\t.ds 8\n");
if(RegBankUsed[1]||options.parms_in_bank1)
- fprintf (asmFile, "\t.area REG_BANK_1\t(REL,OVR,DATA)\n\t.ds 8\n");
+ fprintf (asmFile, "\t.area REG_BANK_1\t(REL,OVR,DATA)\n\t.ds 8\n");
if(RegBankUsed[2])
- fprintf (asmFile, "\t.area REG_BANK_2\t(REL,OVR,DATA)\n\t.ds 8\n");
+ fprintf (asmFile, "\t.area REG_BANK_2\t(REL,OVR,DATA)\n\t.ds 8\n");
if(RegBankUsed[3])
- fprintf (asmFile, "\t.area REG_BANK_3\t(REL,OVR,DATA)\n\t.ds 8\n");
+ fprintf (asmFile, "\t.area REG_BANK_3\t(REL,OVR,DATA)\n\t.ds 8\n");
+ }
+ if(BitBankUsed)
+ {
+ fprintf (asmFile, "%s", iComments2);
+ fprintf (asmFile, "; overlayable bit register bank\n");
+ fprintf (asmFile, "%s", iComments2);
+ fprintf (asmFile, "\t.area BIT_BANK\t(REL,OVR,DATA)\n");
+ fprintf (asmFile, "bits:\n\t.ds 1\n");
+ fprintf (asmFile, "\tb0 = bits[0]\n");
+ fprintf (asmFile, "\tb1 = bits[1]\n");
+ fprintf (asmFile, "\tb2 = bits[2]\n");
+ fprintf (asmFile, "\tb3 = bits[3]\n");
+ fprintf (asmFile, "\tb4 = bits[4]\n");
+ fprintf (asmFile, "\tb5 = bits[5]\n");
+ fprintf (asmFile, "\tb6 = bits[6]\n");
+ fprintf (asmFile, "\tb7 = bits[7]\n");
}
}
* the post_static_name area will immediately follow the static_name
* area.
*/
+ tfprintf (asmFile, "\t!area\n", port->mem.home_name);
tfprintf (asmFile, "\t!area\n", port->mem.static_name); /* MOF */
tfprintf (asmFile, "\t!area\n", port->mem.post_static_name);
tfprintf (asmFile, "\t!area\n", port->mem.static_name);
tfprintf (asmFile, "\t!areahome\n", HOME_NAME);
copyFile (asmFile, home->oFile);
- /* copy over code */
- fprintf (asmFile, "%s", iComments2);
- fprintf (asmFile, "; code\n");
- fprintf (asmFile, "%s", iComments2);
- tfprintf (asmFile, "\t!areacode\n", CODE_NAME);
if (mainf && IFFUNC_HASBODY(mainf->type))
{
- /* entry point @ start of CSEG */
+ /* entry point @ start of HOME */
fprintf (asmFile, "__sdcc_program_startup:\n");
/* put in jump or call to main */
fprintf (asmFile, "\tsjmp .\n");
}
}
+ /* copy over code */
+ fprintf (asmFile, "%s", iComments2);
+ fprintf (asmFile, "; code\n");
+ fprintf (asmFile, "%s", iComments2);
+ tfprintf (asmFile, "\t!areacode\n", options.code_seg);
copyFile (asmFile, code->oFile);
if (port->genAssemblerEnd) {