* Simulator of microcontrollers (z80.cc)
*
* some z80 code base from Karl Bongers karl@turbobit.com
- *
+ *
* Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- *
+ *
* To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
*
*/
return(0);
}
-char *
+const char *
cl_z80::id_string(void)
{
return("unspecified Z80");
cl_z80::inst_length(t_addr addr)
{
int len = 0;
- char *s;
- s = get_disasm_info(addr, &len, NULL, NULL);
+ get_disasm_info(addr, &len, NULL, NULL);
return len;
}
cl_z80::inst_branch(t_addr addr)
{
int b;
- char *s;
- s = get_disasm_info(addr, NULL, &b, NULL);
+ get_disasm_info(addr, NULL, &b, NULL);
return b;
}
}
-char *
+const char *
cl_z80::get_disasm_info(t_addr addr,
int *ret_len,
int *ret_branch,
int *immed_offset)
{
- char *b = NULL;
+ const char *b = NULL;
uint code;
int len = 0;
int immed_n = 0;
return b;
}
-char *
-cl_z80::disass(t_addr addr, char *sep)
+const char *
+cl_z80::disass(t_addr addr, const char *sep)
{
char work[256], temp[20];
- char *buf, *p, *b, *t;
+ const char *b;
+ char *buf, *p, *t;
int len = 0;
int immed_offset = 0;
p= work;
b = get_disasm_info(addr, &len, NULL, &immed_offset);
-
+
if (b == NULL) {
buf= (char*)malloc(30);
strcpy(buf, "UNKNOWN/INVALID");
while (*b)
{
if (*b == '%')
- {
- b++;
- switch (*(b++))
- {
- case 'd': // d jump relative target, signed? byte immediate operand
- sprintf(temp, "#%d", (char)get_mem(MEM_ROM_ID, addr+immed_offset));
- ++immed_offset;
- break;
- case 'w': // w word immediate operand
- sprintf(temp, "#0x%04x",
- (uint)((get_mem(MEM_ROM_ID, addr+immed_offset)) |
- (get_mem(MEM_ROM_ID, addr+immed_offset+1)<<8)) );
- ++immed_offset;
- ++immed_offset;
- break;
- case 'b': // b byte immediate operand
- sprintf(temp, "#0x%02x", (uint)get_mem(MEM_ROM_ID, addr+immed_offset));
- ++immed_offset;
- break;
- default:
- strcpy(temp, "?");
- break;
- }
- t= temp;
- while (*t)
- *(p++)= *(t++);
- }
+ {
+ b++;
+ switch (*(b++))
+ {
+ case 'd': // d jump relative target, signed? byte immediate operand
+ sprintf(temp, "#%d", (char)get_mem(MEM_ROM_ID, addr+immed_offset));
+ ++immed_offset;
+ break;
+ case 'w': // w word immediate operand
+ sprintf(temp, "#0x%04x",
+ (uint)((get_mem(MEM_ROM_ID, addr+immed_offset)) |
+ (get_mem(MEM_ROM_ID, addr+immed_offset+1)<<8)) );
+ ++immed_offset;
+ ++immed_offset;
+ break;
+ case 'b': // b byte immediate operand
+ sprintf(temp, "#0x%02x", (uint)get_mem(MEM_ROM_ID, addr+immed_offset));
+ ++immed_offset;
+ break;
+ default:
+ strcpy(temp, "?");
+ break;
+ }
+ t= temp;
+ while (*t)
+ *(p++)= *(t++);
+ }
else
- *(p++)= *(b++);
+ *(p++)= *(b++);
}
*p= '\0';
buf= (char *)malloc(6+strlen(p)+1);
else
buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
- for (p= work, b= buf; *p != ' '; p++, b++)
- *b= *p;
+ for (p= work, t= buf; *p != ' '; p++, t++)
+ *t= *p;
p++;
- *b= '\0';
+ *t= '\0';
if (sep == NULL)
{
while (strlen(buf) < 6)
- strcat(buf, " ");
+ strcat(buf, " ");
}
else
strcat(buf, sep);
void
-cl_z80::print_regs(class cl_console *con)
+cl_z80::print_regs(class cl_console_base *con)
{
con->dd_printf("SZ-A--P-C Flags= 0x%02x %3d %c ",
- regs.F, regs.F, isprint(regs.F)?regs.F:'.');
+ regs.F, regs.F, isprint(regs.F)?regs.F:'.');
con->dd_printf("A= 0x%02x %3d %c\n",
- regs.A, regs.A, isprint(regs.A)?regs.A:'.');
+ regs.A, regs.A, isprint(regs.A)?regs.A:'.');
con->dd_printf("%c%c-%c--%c-%c\n",
- (regs.F&BIT_S)?'1':'0',
- (regs.F&BIT_Z)?'1':'0',
- (regs.F&BIT_A)?'1':'0',
- (regs.F&BIT_P)?'1':'0',
- (regs.F&BIT_C)?'1':'0');
+ (regs.F&BIT_S)?'1':'0',
+ (regs.F&BIT_Z)?'1':'0',
+ (regs.F&BIT_A)?'1':'0',
+ (regs.F&BIT_P)?'1':'0',
+ (regs.F&BIT_C)?'1':'0');
con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c ",
- regs.BC, ram->get(regs.BC), ram->get(regs.BC),
- isprint(ram->get(regs.BC))?ram->get(regs.BC):'.');
+ regs.BC, ram->get(regs.BC), ram->get(regs.BC),
+ isprint(ram->get(regs.BC))?ram->get(regs.BC):'.');
con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c ",
- regs.DE, ram->get(regs.DE), ram->get(regs.DE),
- isprint(ram->get(regs.DE))?ram->get(regs.DE):'.');
+ regs.DE, ram->get(regs.DE), ram->get(regs.DE),
+ isprint(ram->get(regs.DE))?ram->get(regs.DE):'.');
con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n",
- regs.HL, ram->get(regs.HL), ram->get(regs.HL),
- isprint(ram->get(regs.HL))?ram->get(regs.HL):'.');
+ regs.HL, ram->get(regs.HL), ram->get(regs.HL),
+ isprint(ram->get(regs.HL))?ram->get(regs.HL):'.');
con->dd_printf("IX= 0x%04x [IX]= %02x %3d %c ",
- regs.IX, ram->get(regs.IX), ram->get(regs.IX),
- isprint(ram->get(regs.IX))?ram->get(regs.IX):'.');
+ regs.IX, ram->get(regs.IX), ram->get(regs.IX),
+ isprint(ram->get(regs.IX))?ram->get(regs.IX):'.');
con->dd_printf("IY= 0x%04x [IY]= %02x %3d %c ",
- regs.IY, ram->get(regs.IY), ram->get(regs.IY),
- isprint(ram->get(regs.IY))?ram->get(regs.IY):'.');
+ regs.IY, ram->get(regs.IY), ram->get(regs.IY),
+ isprint(ram->get(regs.IY))?ram->get(regs.IY):'.');
con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
- regs.SP, ram->get(regs.SP), ram->get(regs.SP),
- isprint(ram->get(regs.SP))?ram->get(regs.SP):'.');
-
+ regs.SP, ram->get(regs.SP), ram->get(regs.SP),
+ isprint(ram->get(regs.SP))?ram->get(regs.SP):'.');
+
print_disass(PC, con);
}
case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x77:
case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
return(inst_ld(code));
- case 0x76:
+ case 0x76:
return(inst_halt(code));
case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87: