Merge branch ucsim-034-pre3 to main trunk; new version 0.4

[fw/sdcc] / sim / ucsim / z80.src / regsz80.h

diff --git a/sim/ucsim/z80.src/regsz80.h b/sim/ucsim/z80.src/regsz80.h
index b176a01652929e07cec9786acf3c9dae3b8b40b2..7f85f83df4cea127e89f3db4c61d06904b59ca05 100644 (file)
--- a/sim/ucsim/z80.src/regsz80.h
+++ b/sim/ucsim/z80.src/regsz80.h
@@ -1,6 +1,8 @@
 /*
  * Simulator of microcontrollers (regsz80.h)
  *
+ * some z80 code base from Karl Bongers karl@turbobit.com
+ *
  * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
  * 
  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
@@ -25,8 +27,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 02111-1307, USA. */
 /*@1@*/
 
-#ifndef REGSAVR_HEADER
-#define REGSAVR_HEADER
+#ifndef REGSZ80_HEADER
+#define REGSZ80_HEADER
 
 #include "ddconfig.h"
 
@@ -55,17 +57,33 @@ struct t_regs
   DEF_REGPAIR(BC, bc);
   DEF_REGPAIR(DE, de);
   DEF_REGPAIR(HL, hl);
-  TYPE_UWORD IX;
-  TYPE_UWORD IY;
+  DEF_REGPAIR(IX, ix);
+  DEF_REGPAIR(IY, iy);
   TYPE_UWORD SP;
+  /* there are alternate AF,BC,DE,HL register sets, and a few instructions
+     that swap one for the other */
+  TYPE_UBYTE aA;
+  TYPE_UBYTE aF;
+  DEF_REGPAIR(aBC, a_bc);
+  DEF_REGPAIR(aDE, a_de);
+  DEF_REGPAIR(aHL, a_hl);
+  TYPE_UBYTE iv;  /* interrupt vector, see ed 47 ld A,IV.. */
 };
 
-#define BIT_C  0x01
-#define BIT_P  0x04
-#define BIT_A  0x10
-#define BIT_Z  0x40
-#define BIT_S  0x80
+#define BIT_C  0x01  // carry status(out of bit 7)
+#define BIT_N  0x02  // Not addition: subtract status(1 after subtract).
+#define BIT_P  0x04  // parity/overflow, 1=even, 0=odd parity.  arith:1=overflow
+#define BIT_A  0x10  // aux carry status(out of bit 3)
+#define BIT_Z  0x40  // zero status, 1=zero, 0=nonzero
+#define BIT_S  0x80  // sign status(value of bit 7)
+#define BIT_ALL        (BIT_C |BIT_N |BIT_P |BIT_A |BIT_Z |BIT_S)  // all bits
 
+#define BITPOS_C 0    // 1
+#define BITPOS_SUB 1  // 2H
+#define BITPOS_P 2    // 4H
+#define BITPOS_A 4    // 10H
+#define BITPOS_Z 6    // 40H
+#define BITPOS_S 7    // 80H
 
 #endif