xa51, work in progress

[fw/sdcc] / sim / ucsim / xa.src / xa_bit.cc

diff --git a/sim/ucsim/xa.src/xa_bit.cc b/sim/ucsim/xa.src/xa_bit.cc
new file mode 100755 (executable)
index 0000000..5ed3cc6
--- /dev/null
+++ b/sim/ucsim/xa.src/xa_bit.cc
@@ -0,0 +1,91 @@
+{CPU_XA, 0x33B, "ETI1"}, /* TX interrupt enable 1 */
+{CPU_XA, 0x33A, "ERI1"}, /* RX interrupt enable 1 */
+{CPU_XA, 0x339, "ETI0"}, /* TX interrupt enable 0 */
+{CPU_XA, 0x338, "ERI0"}, /* RX interrupt enable 0 */
+{CPU_XA, 0x337, "EA"}, /* global int. enable */
+{CPU_XA, 0x334, "ET2"}, /* timer 2 interrupt */
+{CPU_XA, 0x333, "ET1"}, /* timer 1 interrupt */
+{CPU_XA, 0x332, "EX1"}, /* external interrupt 1 */
+{CPU_XA, 0x331, "ET0"}, /* timer 0 interrupt */
+{CPU_XA, 0x330, "EX0"}, /* external interrupt 0 */
+{CPU_XA, 0x221, "PD"}, /* power down */
+{CPU_XA, 0x220, "IDL"},
+{CPU_XA, 0x20F, "SM"},
+{CPU_XA, 0x20E, "TM"},
+{CPU_XA, 0x20D, "RS1"},
+{CPU_XA, 0x20C, "RS0"},
+{CPU_XA, 0x20B, "IM3"},
+{CPU_XA, 0x20A, "IM2"},
+{CPU_XA, 0x209, "IM1"},
+{CPU_XA, 0x208, "IM0"},
+{CPU_XA, 0x307, "S0M0"},
+{CPU_XA, 0x306, "S0M1"},
+{CPU_XA, 0x305, "S0M2"},
+{CPU_XA, 0x304, "R0EN"},
+{CPU_XA, 0x303, "T0B8"},
+{CPU_XA, 0x302, "R0B8"},
+{CPU_XA, 0x301, "TI0"}, /* serial port 0 tx ready */
+{CPU_XA, 0x300, "RI0"}, /* serial port 0 rx ready */
+{CPU_XA, 0x30B, "FE0"},
+{CPU_XA, 0x30A, "BR0"},
+{CPU_XA, 0x309, "OE0"},
+{CPU_XA, 0x308, "STINT0"},
+{CPU_XA, 0x327, "S1M0"},
+{CPU_XA, 0x326, "S1M1"},
+{CPU_XA, 0x325, "S1M2"},
+{CPU_XA, 0x324, "R1EN"},
+{CPU_XA, 0x323, "T1B8"},
+{CPU_XA, 0x322, "R1B8"},
+{CPU_XA, 0x321, "TI1"}, /* serial port 0 tx ready */
+{CPU_XA, 0x320, "RI1"}, /* serial port 0 rx ready */
+{CPU_XA, 0x32B, "FE1"},
+{CPU_XA, 0x32A, "BR1"},
+{CPU_XA, 0x329, "OE1"},
+{CPU_XA, 0x328, "STINT1"},
+{CPU_XA, 0x356, "SWR7"},
+{CPU_XA, 0x355, "SWR6"},
+{CPU_XA, 0x354, "SWR5"},
+{CPU_XA, 0x353, "SWR4"},
+{CPU_XA, 0x352, "SWR3"},
+{CPU_XA, 0x351, "SWR2"},
+{CPU_XA, 0x350, "SWR1"},
+{CPU_XA, 0x2C7, "TF2"},
+{CPU_XA, 0x2C6, "EXF2"},
+{CPU_XA, 0x2C5, "RCLK0"},
+{CPU_XA, 0x2C4, "TCLK0"},
+{CPU_XA, 0x2CD, "RCLK1"},
+{CPU_XA, 0x2CC, "TCLK1"},
+{CPU_XA, 0x2C3, "EXEN2"},
+{CPU_XA, 0x2C2, "TR2"},
+{CPU_XA, 0x2C1, "CT2"},
+{CPU_XA, 0x2C0, "CPRL2"},
+{CPU_XA, 0x2C9, "T2OE"},
+{CPU_XA, 0x2C8, "DCEN"},
+{CPU_XA, 0x287, "TF1"},
+{CPU_XA, 0x286, "TR1"},
+{CPU_XA, 0x285, "TF0"},
+{CPU_XA, 0x284, "TR0"},
+{CPU_XA, 0x283, "IE1"},
+{CPU_XA, 0x282, "IT1"},
+{CPU_XA, 0x281, "IE0"},
+{CPU_XA, 0x280, "IT0"},
+{CPU_XA, 0x28A, "T1OE"},
+{CPU_XA, 0x288, "T0OE"},
+{CPU_XA, 0x2FF, "PRE2"},
+{CPU_XA, 0x2FE, "PRE1"},
+{CPU_XA, 0x2FD, "PRE0"},
+{CPU_XA, 0x2FA, "WDRUN"},
+{CPU_XA, 0x2F9, "WDTOF"},
+{CPU_XA, 0x2F8, "WDMOD"},
+{CPU_XA, 0x388, "WR1"},
+{CPU_XA, 0x38F, "T2EX"},
+{CPU_XA, 0x38C, "RXD1"},
+{CPU_XA, 0x38D, "TXD1"},
+{CPU_XA, 0x398, "RXD0"},
+{CPU_XA, 0x399, "TXD0"},
+{CPU_XA, 0x39A, "INT0"},
+{CPU_XA, 0x39B, "INT1"},
+{CPU_XA, 0x39C, "T0"},
+{CPU_XA, 0x39D, "T1"},
+{CPU_XA, 0x39E, "WR"},
+{CPU_XA, 0x39F, "RD"},