*** empty log message ***

[fw/sdcc] / sim / ucsim / xa.src / glob.h

diff --git a/sim/ucsim/xa.src/glob.h b/sim/ucsim/xa.src/glob.h
index 16b9e3f793239e2526141e9dd7c39306ad58b339..5e992ec87299b18fb6654075587eeecd24a8d41d 100644 (file)
--- a/sim/ucsim/xa.src/glob.h
+++ b/sim/ucsim/xa.src/glob.h
@@ -3,9 +3,10 @@
  *
  * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
  *
- * Written by Karl Bongers karl@turbobit.com
- * 
  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ * Other contributors include:
+ *   Karl Bongers karl@turbobit.com,
+ *   Johan Knol 
  *
  */
 
@@ -32,83 +33,94 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 
 #include "stypes.h"
 
-
-#if 0
-enum {
-  REG,
-  IND_REG,
-  IND_REG_PLUS,
-  IND_REG_OFFSET,
-  DIRECT,
-  DATA8,
-  DATA16
-};
-#endif
-
+/* this needs to match char *op_mnemonic_str[] definition in glob.cc */
 enum {
 BAD_OPCODE=0,
 ADD,
 ADDC,
-SUB,
-SUBB,
-CMP,
-AND,
-OR,
-XOR,
 ADDS,
-NEG,
-SEXT,
-MUL,
+AND,
+ANL,
+ASL,
+ASR,
+BCC,
+BCS,
+BEQ,
+BG,
+BGE,
+BGT,
+BKPT,
+BL,
+BLE,
+BLT,
+BMI,
+BNE,
+BNV,
+BOV,
+BPL,
+BR,
+CALL,
+CJNE,
+CLR,
+CMP,
+CPL,
+DA,
 DIV_w,
 DIV_d,
 DIVU_b,
 DIVU_w,
 DIVU_d,
-DA,
-ASL,
-ASR,
+DJNZ,
+FCALL,
+FJMP,
+JB,
+JBC,
+JMP,
+JNB,
+JNZ,
+JZ,
 LEA,
-CPL,
 LSR,
+MOV,
+MOVC,
+MOVS,
+MOVX,
+MUL_w,
+MULU_b,
+MULU_w,
+NEG,
+NOP,
 NORM,
+OR,
+ORL,
+POP,
+POPU,
+PUSH,
+PUSHU,
+RESET,
+RET,
+RETI,
 RL,
 RLC,
 RR,
 RRC,
-MOVS,
-MOVC,
-MOVX,
-PUSH,
-POP,
-XCH,
 SETB,
-CLR,
-MOV,
-ANL,
-ORL,
-BR,
-JMP,
-CALL,
-RET,
-Bcc,
-JB,
-JNB,
-CJNE,
-DJNZ,
-JZ,
-JNZ,
-NOP,
-BKPT,
+SEXT,
+SUB,
+SUBB,
 TRAP,
-RESET,
-FCALL,
-FJMP,
+XCH,
+XOR,
 };
 
 extern char *op_mnemonic_str[];
 
+/* this classifies the operands and is used in the dissassembly
+   to print the operands.  Its also used in the simulation to characterize
+   the op-code function.
+ */   
 enum op_operands {
-   // the repeating common parameter encoding for ADD, ADDC, SUB, AND...
+   // the repeating parameter encoding for ADD, ADDC, SUB, SUBB, AND, XOR, ...
   REG_REG         ,
   REG_IREG        ,
   IREG_REG        ,
@@ -136,7 +148,8 @@ enum op_operands {
 // odd-ball ones
   NO_OPERANDS,  // for NOP
   C_BIT,
-  NOTC_BIT,
+  C_NOTBIT,
+  DATA4,
   REG_DATA4,
   IREG_DATA4,
   IREGINC_DATA4,
@@ -144,28 +157,49 @@ enum op_operands {
   IREGOFF16_DATA4,
   DIRECT_DATA4,
 
-  REG_ALONE,
+  REG,
+  IREG,
+  BIT_ALONE,
+  DIRECT,
+  RLIST,
   ADDR24,
+  BIT_REL8,
   REG_REL8,
-  DIRECT_REL8
+  DIRECT_REL8,
+  REG_REGOFF8,
+  REG_REGOFF16,
+
+  REL8,
+  REL16,
+
+  REG_DIRECT_REL8,
+  REG_DATA8_REL8,
+  REG_DATA16_REL8,
+  IREG_DATA8_REL8,
+  IREG_DATA16_REL8,
+
+  A_APLUSDPTR,
+  A_APLUSPC
 };
 
 // table of dissassembled instructions
 struct xa_dis_entry
 {
-  uint  code, mask;
-  char  branch;
-  uchar length;
-//  enum op_mnemonic mnemonic;
-//  enum op_operands operands;
-  int mnemonic;
-  int operands;
+  uint is1byte; /* only grab 1 byte for table lookup(most are 2 bytes) */
+  uint code;    /* bits in opcode used to match table entry(with mask) */
+  uint mask;    /* mask used on .code to match up a common opcode */
+  char branch;  /* used by main app to implement "next" around calls */
+  uchar length; /* total length of opcode, used by dissasembler and main app */
+  int mnemonic; /* type of opcode(ADD, ADDC...) */
+  int operands; /* unique classification of operands: Rd,Rs = REG_REG,... */
 };
 
 extern struct dis_entry glob_disass_xa[];
 
 extern struct xa_dis_entry disass_xa[];
 
+extern struct name_entry sfr_tabXA51[];
+extern struct name_entry bit_tabXA51[];
 #endif
 
 /* End of xa.src/glob.h */