*** empty log message ***

[fw/sdcc] / sim / ucsim / xa.src / glob.h

diff --git a/sim/ucsim/xa.src/glob.h b/sim/ucsim/xa.src/glob.h
index 16b9e3f793239e2526141e9dd7c39306ad58b339..49bb834ccad5eea9be6b80692ff636dade8c001f 100644 (file)
--- a/sim/ucsim/xa.src/glob.h
+++ b/sim/ucsim/xa.src/glob.h
@@ -3,9 +3,10 @@
  *
  * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
  *
- * Written by Karl Bongers karl@turbobit.com
- * 
  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ * Other contributors include:
+ *   Karl Bongers karl@turbobit.com,
+ *   Johan Knol 
  *
  */
 
@@ -32,19 +33,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 
 #include "stypes.h"
 
-
-#if 0
-enum {
-  REG,
-  IND_REG,
-  IND_REG_PLUS,
-  IND_REG_OFFSET,
-  DIRECT,
-  DATA8,
-  DATA16
-};
-#endif
-
+/* this needs to match char *op_mnemonic_str[] definition in glob.cc */
 enum {
 BAD_OPCODE=0,
 ADD,
@@ -79,19 +68,36 @@ MOVS,
 MOVC,
 MOVX,
 PUSH,
+PUSHU,
 POP,
+POPU,
 XCH,
 SETB,
 CLR,
 MOV,
 ANL,
 ORL,
-BR,
 JMP,
 CALL,
 RET,
-Bcc,
+RETI,
+BCC,
+BCS,
+BEQ,
+BG,
+BGE,
+BGT,
+BL,
+BLE,
+BLT,
+BMI,
+BNE,
+BNV,
+BOV,
+BPL,
+BR,
 JB,
+JBC,
 JNB,
 CJNE,
 DJNZ,
@@ -103,12 +109,17 @@ TRAP,
 RESET,
 FCALL,
 FJMP,
+IREG,
 };
 
 extern char *op_mnemonic_str[];
 
+/* this classifies the operands and is used in the dissassembly
+   to print the operands.  Its also used in the simulation to characterize
+   the op-code function.
+ */   
 enum op_operands {
-   // the repeating common parameter encoding for ADD, ADDC, SUB, AND...
+   // the repeating parameter encoding for ADD, ADDC, SUB, SUBB, AND, XOR, ...
   REG_REG         ,
   REG_IREG        ,
   IREG_REG        ,
@@ -136,7 +147,7 @@ enum op_operands {
 // odd-ball ones
   NO_OPERANDS,  // for NOP
   C_BIT,
-  NOTC_BIT,
+  C_NOTBIT,
   REG_DATA4,
   IREG_DATA4,
   IREGINC_DATA4,
@@ -145,9 +156,24 @@ enum op_operands {
   DIRECT_DATA4,
 
   REG_ALONE,
+  IREG_ALONE,
+  BIT_ALONE,
+  BIT_REL8,
+  DIRECT_ALONE,
+  RLIST,
   ADDR24,
   REG_REL8,
-  DIRECT_REL8
+  DIRECT_REL8,
+
+  REL8,
+  REL16,
+
+  REG_DIRECT_REL8,
+  REG_DATA8_REL8,
+  REG_DATA16_REL8,
+  IREG_DATA8_REL8,
+  IREG_DATA16_REL8
+
 };
 
 // table of dissassembled instructions
@@ -156,8 +182,6 @@ struct xa_dis_entry
   uint  code, mask;
   char  branch;
   uchar length;
-//  enum op_mnemonic mnemonic;
-//  enum op_operands operands;
   int mnemonic;
   int operands;
 };