work in progress

[fw/sdcc] / sim / ucsim / xa.src / glob.h

diff --git a/sim/ucsim/xa.src/glob.h b/sim/ucsim/xa.src/glob.h
index 090675cb765237a72a2312ba99c19c63da2cba0c..008bef38877a5af22005061b64574e05ac04e111 100644 (file)
--- a/sim/ucsim/xa.src/glob.h
+++ b/sim/ucsim/xa.src/glob.h
@@ -6,7 +6,7 @@
  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
  * Other contributors include:
  *   Karl Bongers karl@turbobit.com,
- *   Johan Knol 
+ *   Johan Knol johan.knol@iduna.nl
  *
  */
 
@@ -147,10 +147,12 @@ enum op_operands {
 
 // odd-ball ones
   NO_OPERANDS,  // for NOP
-  C_BIT,
-  C_NOTBIT,
+  CY_BIT,
+  BIT_CY,
+  CY_NOTBIT,
   DATA4,
   REG_DATA4,
+  REG_DATA5,
   IREG_DATA4,
   IREGINC_DATA4,
   IREGOFF8_DATA4,
@@ -161,6 +163,7 @@ enum op_operands {
   IREG,
   BIT_ALONE,
   DIRECT,
+  DIRECT_DIRECT,
   RLIST,
   ADDR24,
   BIT_REL8,
@@ -169,6 +172,9 @@ enum op_operands {
   REG_REGOFF8,
   REG_REGOFF16,
 
+  REG_USP,
+  USP_REG,
+
   REL8,
   REL16,
 
@@ -176,18 +182,22 @@ enum op_operands {
   REG_DATA8_REL8,
   REG_DATA16_REL8,
   IREG_DATA8_REL8,
-  IREG_DATA16_REL8
+  IREG_DATA16_REL8,
 
+  A_APLUSDPTR,
+  A_APLUSPC
 };
 
 // table of dissassembled instructions
 struct xa_dis_entry
 {
-  uint  code, mask;
-  char  branch;
-  uchar length;
-  int mnemonic;
-  int operands;
+  uint is1byte; /* only grab 1 byte for table lookup(most are 2 bytes) */
+  uint code;    /* bits in opcode used to match table entry(with mask) */
+  uint mask;    /* mask used on .code to match up a common opcode */
+  char branch;  /* used by main app to implement "next" around calls */
+  uchar length; /* total length of opcode, used by dissasembler and main app */
+  int mnemonic; /* type of opcode(ADD, ADDC...) */
+  int operands; /* unique classification of operands: Rd,Rs = REG_REG,... */
 };
 
 extern struct dis_entry glob_disass_xa[];