// local
#include "uc89c51rcl.h"
#include "regs51.h"
+#include "pcacl.h"
t_uc89c51r::t_uc89c51r(int Itype, int Itech, class cl_sim *asim):
t_uc51r(Itype, Itech, asim)
{
- it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF4, 0x0033, false,
+ /*it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF4, 0x0033, false,
"PCA module #4"));
it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF3, 0x0033, false,
"PCA module #3"));
it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF0, 0x0033, false,
"PCA module #0"));
it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCF, 0x0033, false,
- "PCA counter"));
+ "PCA counter"));*/
}
void
-t_uc89c51r::reset(void)
+t_uc89c51r::mk_hw_elements(void)
{
- t_uc51r::reset();
- mem(MEM_SFR)->set_bit1(CCAPM0, bmECOM);
- mem(MEM_SFR)->set_bit1(CCAPM1, bmECOM);
- mem(MEM_SFR)->set_bit1(CCAPM2, bmECOM);
- mem(MEM_SFR)->set_bit1(CCAPM3, bmECOM);
- mem(MEM_SFR)->set_bit1(CCAPM4, bmECOM);
- t0_overflows= 0;
- dpl0= dph0= dpl1= dph1= 0;
- set_mem(MEM_SFR, IPH, 0);
+ class cl_hw *h;
+
+ t_uc51r::mk_hw_elements();
+ hws->add(h= new cl_pca(this, 0));
+ h->init();
+ /*hws->add(h= new cl_pca(this, 1));
+ h->init();
+ hws->add(h= new cl_pca(this, 2));
+ h->init();
+ hws->add(h= new cl_pca(this, 3));
+ h->init();
+ hws->add(h= new cl_pca(this, 4));
+ h->init();*/
+ hws->add(h= new cl_89c51r_dummy_hw(this));
+ h->init();
}
-void
-t_uc89c51r::proc_write(uchar *addr)
-{
- t_uc51r::proc_write(addr);
-
- if (addr == &(MEM(MEM_SFR)[CCAP0L]))
- mem(MEM_SFR)->set_bit0(CCAPM0, bmECOM);
- if (addr == &(MEM(MEM_SFR)[CCAP0H]))
- mem(MEM_SFR)->set_bit1(CCAPM0, bmECOM);
-
- if (addr == &(MEM(MEM_SFR)[CCAP1L]))
- mem(MEM_SFR)->set_bit0(CCAPM1, bmECOM);
- if (addr == &(MEM(MEM_SFR)[CCAP1H]))
- mem(MEM_SFR)->set_bit1(CCAPM1, bmECOM);
- if (addr == &(MEM(MEM_SFR)[CCAP2L]))
- mem(MEM_SFR)->set_bit0(CCAPM2, bmECOM);
- if (addr == &(MEM(MEM_SFR)[CCAP2H]))
- mem(MEM_SFR)->set_bit1(CCAPM2, bmECOM);
-
- if (addr == &(MEM(MEM_SFR)[CCAP3L]))
- mem(MEM_SFR)->set_bit0(CCAPM3, bmECOM);
- if (addr == &(MEM(MEM_SFR)[CCAP3H]))
- mem(MEM_SFR)->set_bit1(CCAPM3, bmECOM);
-
- if (addr == &(MEM(MEM_SFR)[CCAP4L]))
- mem(MEM_SFR)->set_bit0(CCAPM4, bmECOM);
- if (addr == &(MEM(MEM_SFR)[CCAP4H]))
- mem(MEM_SFR)->set_bit1(CCAPM4, bmECOM);
-
- if (addr == &(MEM(MEM_SFR)[AUXR]))
- mem(MEM_SFR)->set_bit0(AUXR, 0x04);
-}
-
-uchar
-t_uc89c51r::read(uchar *addr)
+void
+t_uc89c51r::reset(void)
{
- return(t_uc51r::read(addr));
+ t_uc51r::reset();
+ sfr->set_bit1(CCAPM0, bmECOM);
+ sfr->set_bit1(CCAPM1, bmECOM);
+ sfr->set_bit1(CCAPM2, bmECOM);
+ sfr->set_bit1(CCAPM3, bmECOM);
+ sfr->set_bit1(CCAPM4, bmECOM);
+ //t0_overflows= 0;
+ dpl0= dph0= dpl1= dph1= 0;
+ sfr->set(IPH, 0);
}
int
{
uchar l, h;
- l= get_mem(MEM_SFR, IP) & ie_mask;
- h= get_mem(MEM_SFR, IPH) & ie_mask;
+ l= sfr->get(IP) & ie_mask;
+ h= sfr->get(IPH) & ie_mask;
if (!h && !l)
return(0);
if (!h && l)
void
t_uc89c51r::pre_inst(void)
{
- if (get_mem(MEM_SFR, AUXR1) & bmDPS)
+ if (sfr->get(AUXR1) & bmDPS)
{
- set_mem(MEM_SFR, DPL, dpl1);
- set_mem(MEM_SFR, DPH, dph1);
+ sfr->set(DPL, dpl1);
+ sfr->set(DPH, dph1);
}
else
{
- set_mem(MEM_SFR, DPL, dpl0);
- set_mem(MEM_SFR, DPH, dph0);
+ sfr->set(DPL, dpl0);
+ sfr->set(DPH, dph0);
}
+ t_uc51r::pre_inst();
}
void
t_uc89c51r::post_inst(void)
{
- if (get_mem(MEM_SFR, AUXR1) & bmDPS)
+ if (sfr->get(AUXR1) & bmDPS)
{
- dpl1= get_mem(MEM_SFR, DPL);
- dph1= get_mem(MEM_SFR, DPH);
+ dpl1= sfr->get(DPL);
+ dph1= sfr->get(DPH);
}
else
{
- dpl0= get_mem(MEM_SFR, DPL);
- dph0= get_mem(MEM_SFR, DPH);
+ dpl0= sfr->get(DPL);
+ dph0= sfr->get(DPH);
}
+ t_uc51r::post_inst();
}
/*
- * Simulating timers
- *
- * Calling inherited method to simulate timer #0, #1, #2 and then
- * simulating Programmable Counter Array
*/
-int
-t_uc89c51r::do_timers(int cycles)
-{
- int res;
-
- if ((res= t_uc51r::do_timers(cycles)) != resGO)
- return(res);
- return(do_pca(cycles));
-}
+cl_89c51r_dummy_hw::cl_89c51r_dummy_hw(class cl_uc *auc):
+ cl_hw(auc, HW_DUMMY, 0, "_89c51r_dummy")
+{}
int
-t_uc89c51r::t0_overflow(void)
+cl_89c51r_dummy_hw::init(void)
{
- uchar cmod= get_mem(MEM_SFR, CMOD) & (bmCPS0|bmCPS1);
-
- if (cmod == bmCPS1)
- t0_overflows++;
- return(0);
-}
-
-
-/*
- * Simulating Programmable Counter Array
- */
-
-int
-t_uc89c51r::do_pca(int cycles)
-{
- int ret= resGO;
- uint ccon= get_mem(MEM_SFR, CCON);
-
- if (!(ccon & bmCR))
- return(resGO);
- if (state == stIDLE &&
- (ccon & bmCIDL))
- return(resGO);
-
- switch (get_mem(MEM_SFR, CMOD) & (bmCPS1|bmCPS0))
- {
- case 0:
- ret= do_pca_counter(cycles);
- break;
- case bmCPS0:
- ret= do_pca_counter(cycles*3);
- break;
- case bmCPS1:
- ret= do_pca_counter(t0_overflows);
- t0_overflows= 0;
- break;
- case (bmCPS0|bmCPS1):
- if ((prev_p1 & bmECI) != 0 &
- (get_mem(MEM_SFR, P1) & bmECI) == 0)
- do_pca_counter(1);
- break;
- }
- return(ret);
-}
-
-int
-t_uc89c51r::do_pca_counter(int cycles)
-{
- while (cycles--)
+ class cl_mem *sfr= uc->mem(MEM_SFR);
+ if (!sfr)
{
- if (++(MEM(MEM_SFR)[CL]) == 0)
- {
- if (++(MEM(MEM_SFR)[CH]) == 0)
- {
- /* CH,CL overflow */
- mem(MEM_SFR)->set_bit1(CCON, bmCF);
- do_pca_module(0);
- do_pca_module(1);
- do_pca_module(2);
- do_pca_module(3);
- do_pca_module(4);
- }
- }
+ fprintf(stderr, "No SFR to register %s[%d] into\n", id_string, id);
}
- return(resGO);
+ //auxr= sfr->register_hw(AUXR, this, 0);
+ register_cell(sfr, AUXR, &auxr, wtd_restore);
+ return(0);
}
-int
-t_uc89c51r::do_pca_module(int nr)
+void
+cl_89c51r_dummy_hw::write(class cl_cell *cell, t_mem *val)
{
- uchar CCAPM[5]= {0xda, 0xdb, 0xdc, 0xdd, 0xde};
- uchar CCAPL[5]= {0xea, 0xeb, 0xec, 0xed, 0xee};
- uchar CCAPH[5]= {0xfa, 0xfb, 0xfc, 0xfd, 0xfe};
- uchar bmCEX[5]= {bmCEX0, bmCEX1, bmCEX2, bmCEX3, bmCEX4};
- uchar bmCCF[5]= {bmCCF0, bmCCF1, bmCCF2, bmCCF3, bmCCF4};
- uchar ccapm= get_mem(MEM_SFR, CCAPM[nr]);
- uint p1= get_mem(MEM_SFR, P1);
-
- if (
- ((ccapm & bmCAPP) &&
- (prev_p1 & bmCEX[nr]) == 0 &&
- (p1 & bmCEX[nr]) != 0)
- ||
- ((ccapm & bmCAPN) &&
- (prev_p1 & bmCEX[nr]) != 0 &&
- (p1 & bmCEX[nr]) == 0)
- )
- {
- /* Capture */
- MEM(MEM_SFR)[CCAPL[nr]]= MEM(MEM_SFR)[CL];
- MEM(MEM_SFR)[CCAPH[nr]]= MEM(MEM_SFR)[CH];
- mem(MEM_SFR)->set_bit1(CCON, bmCCF[nr]);
- }
-
- if (ccapm & bmECOM)
- {
- /* Comparator enabled */
- if (MEM(MEM_SFR)[CL] == MEM(MEM_SFR)[CCAPL[nr]] &&
- MEM(MEM_SFR)[CH] == MEM(MEM_SFR)[CCAPH[nr]])
- {
- /* Match */
- if (nr == 4 &&
- (MEM(MEM_SFR)[CMOD] & bmWDTE))
- {
- reset();
- }
- mem(MEM_SFR)->set_bit1(CCON, bmCCF[nr]);
- if (ccapm & bmTOG)
- {
- /* Toggle */
- MEM(MEM_SFR)[P1]^= bmCEX[nr];
- }
- }
- if (ccapm & bmPWM)
- {
- /* PWM */
- if (MEM(MEM_SFR)[CL] == 0)
- MEM(MEM_SFR)[CCAPL[nr]]= MEM(MEM_SFR)[CCAPH[nr]];
- if (MEM(MEM_SFR)[CL] < MEM(MEM_SFR)[CCAPL[nr]])
- MEM(MEM_SFR)[P1]&= ~(bmCEX[nr]);
- else
- mem(MEM_SFR)->set_bit1(P1, bmCEX[nr]);
- }
- }
-
- return(resGO);
+ if (cell == auxr)
+ auxr->set_bit0(0x04);
}