* Simulator of microcontrollers (uc89c51r.cc)
*
* Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- *
+ *
* To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
*
*/
#include "ddconfig.h"
#include <stdio.h>
+#include <ctype.h>
// local
#include "uc89c51rcl.h"
#include "regs51.h"
+#include "pcacl.h"
+#include "wdtcl.h"
-t_uc89c51r::t_uc89c51r(int Itype, int Itech, class cl_sim *asim):
- t_uc51r(Itype, Itech, asim)
+cl_uc89c51r::cl_uc89c51r(int Itype, int Itech, class cl_sim *asim):
+ cl_uc51r(Itype, Itech, asim)
{
- it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF4, 0x0033, false,
- "PCA module #4"));
- it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF3, 0x0033, false,
- "PCA module #3"));
- it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF2, 0x0033, false,
- "PCA module #2"));
- it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF1, 0x0033, false,
- "PCA module #1"));
- it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF0, 0x0033, false,
- "PCA module #0"));
- it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCF, 0x0033, false,
- "PCA counter"));
}
void
-t_uc89c51r::reset(void)
+cl_uc89c51r::mk_hw_elements(void)
{
- t_uc51r::reset();
- mem(MEM_SFR)->set_bit1(CCAPM0, bmECOM);
- mem(MEM_SFR)->set_bit1(CCAPM1, bmECOM);
- mem(MEM_SFR)->set_bit1(CCAPM2, bmECOM);
- mem(MEM_SFR)->set_bit1(CCAPM3, bmECOM);
- mem(MEM_SFR)->set_bit1(CCAPM4, bmECOM);
- t0_overflows= 0;
- dpl0= dph0= dpl1= dph1= 0;
- set_mem(MEM_SFR, IPH, 0);
+ class cl_hw *h;
+
+ cl_uc52::mk_hw_elements();
+ hws->add(h= new cl_wdt(this, 0x3fff));
+ h->init();
+ hws->add(h= new cl_pca(this, 0));
+ h->init();
+ hws->add(h= new cl_89c51r_dummy_hw(this));
+ h->init();
}
void
-t_uc89c51r::proc_write(uchar *addr)
+cl_uc89c51r::make_memories(void)
{
- t_uc51r::proc_write(addr);
-
- if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP0L]))
- mem(MEM_SFR)->set_bit0(CCAPM0, bmECOM);
- if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP0H]))
- mem(MEM_SFR)->set_bit1(CCAPM0, bmECOM);
-
- if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP1L]))
- mem(MEM_SFR)->set_bit0(CCAPM1, bmECOM);
- if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP1H]))
- mem(MEM_SFR)->set_bit1(CCAPM1, bmECOM);
-
- if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP2L]))
- mem(MEM_SFR)->set_bit0(CCAPM2, bmECOM);
- if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP2H]))
- mem(MEM_SFR)->set_bit1(CCAPM2, bmECOM);
-
- if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP3L]))
- mem(MEM_SFR)->set_bit0(CCAPM3, bmECOM);
- if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP3H]))
- mem(MEM_SFR)->set_bit1(CCAPM3, bmECOM);
-
- if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP4L]))
- mem(MEM_SFR)->set_bit0(CCAPM4, bmECOM);
- if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP4H]))
- mem(MEM_SFR)->set_bit1(CCAPM4, bmECOM);
-
- if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[AUXR]))
- mem(MEM_SFR)->set_bit0(AUXR, 0x04);
+ cl_uc52::make_memories();
}
-uchar
-t_uc89c51r::read(uchar *addr)
+
+void
+cl_uc89c51r::reset(void)
{
- return(t_uc51r::read(addr));
+ cl_uc51r::reset();
+ sfr->set_bit1(CCAPM0, bmECOM);
+ sfr->set_bit1(CCAPM1, bmECOM);
+ sfr->set_bit1(CCAPM2, bmECOM);
+ sfr->set_bit1(CCAPM3, bmECOM);
+ sfr->set_bit1(CCAPM4, bmECOM);
+ //t0_overflows= 0;
+ dpl0= dph0= dpl1= dph1= 0;
+ sfr->write(IPH, 0);
}
int
-t_uc89c51r::it_priority(uchar ie_mask)
+cl_uc89c51r::it_priority(uchar ie_mask)
{
uchar l, h;
- l= get_mem(MEM_SFR, IP) & ie_mask;
- h= get_mem(MEM_SFR, IPH) & ie_mask;
+ l= sfr->get(IP) & ie_mask;
+ h= sfr->get(IPH) & ie_mask;
if (!h && !l)
return(0);
if (!h && l)
}
void
-t_uc89c51r::pre_inst(void)
+cl_uc89c51r::pre_inst(void)
{
- if (get_mem(MEM_SFR, AUXR1) & bmDPS)
+ //printf("pre dptr0:%02X%02X dptr1:%02X%02X\n", dph0, dpl0, dph1, dpl1);
+ dps = (sfr->get(AUXR1) & bmDPS);
+ if (dps)
{
- set_mem(MEM_SFR, DPL, dpl1);
- set_mem(MEM_SFR, DPH, dph1);
+ sfr->set(DPL, dpl1);
+ sfr->set(DPH, dph1);
}
else
{
- set_mem(MEM_SFR, DPL, dpl0);
- set_mem(MEM_SFR, DPH, dph0);
+ sfr->set(DPL, dpl0);
+ sfr->set(DPH, dph0);
}
+ cl_uc51r::pre_inst();
}
void
-t_uc89c51r::post_inst(void)
+cl_uc89c51r::post_inst(void)
{
- if (get_mem(MEM_SFR, AUXR1) & bmDPS)
+ if (dps)
+ {
+ dpl1= sfr->get(DPL);
+ dph1= sfr->get(DPH);
+ }
+ else
+ {
+ dpl0= sfr->get(DPL);
+ dph0= sfr->get(DPH);
+ }
+ dps = (sfr->get(AUXR1) & bmDPS);
+ if (dps)
{
- dpl1= get_mem(MEM_SFR, DPL);
- dph1= get_mem(MEM_SFR, DPH);
+ sfr->set(DPL, dpl1);
+ sfr->set(DPH, dph1);
}
else
{
- dpl0= get_mem(MEM_SFR, DPL);
- dph0= get_mem(MEM_SFR, DPH);
+ sfr->set(DPL, dpl0);
+ sfr->set(DPH, dph0);
}
+ //printf("post dptr0:%02X%02X dptr1:%02X%02X\n", dph0, dpl0, dph1, dpl1);
+ cl_uc51r::post_inst();
}
-/*
- * Simulating timers
- *
- * Calling inherited method to simulate timer #0, #1, #2 and then
- * simulating Programmable Counter Array
- */
-
-int
-t_uc89c51r::do_timers(int cycles)
-{
- int res;
-
- if ((res= t_uc51r::do_timers(cycles)) != resGO)
- return(res);
- return(do_pca(cycles));
-}
-
-int
-t_uc89c51r::t0_overflow(void)
+void
+cl_uc89c51r::print_regs(class cl_console_base *con)
{
- uchar cmod= get_mem(MEM_SFR, CMOD) & (bmCPS0|bmCPS1);
-
- if (cmod == bmCPS1)
- t0_overflows++;
- return(0);
+ t_addr start;
+ uchar data, acc, dps;
+
+ start= psw->get() & 0x18;
+ //dump_memory(iram, &start, start+7, 8, /*sim->cmd_out()*/con, sim);
+ iram->dump(start, start+7, 8, con);
+ start= psw->get() & 0x18;
+ data= iram->get(iram->get(start));
+ con->dd_printf("%06x %02x %c",
+ iram->get(start), data, isprint(data)?data:'.');
+
+ acc= sfr->get(ACC);
+ con->dd_printf(" ACC= 0x%02x %3d %c B= 0x%02x", acc, acc,
+ isprint(acc)?(acc):'.', sfr->get(B));
+ //eram2xram();
+ dps = sfr->get(AUXR1) & bmDPS;
+ data= xram->get(dph0*256+dpl0);
+ con->dd_printf(" %cDPTR0= 0x%02x%02x @DPTR0= 0x%02x %3d %c",
+ dps?' ':'*', dph0, dpl0,
+ data, data, isprint(data)?data:'.');
+ data= xram->get(dph1*256+dpl1);
+ con->dd_printf(" %cDPTR1= 0x%02x%02x @DPTR1= 0x%02x %3d %c\n",
+ dps?'*':' ', dph1, dpl1,
+ data, data, isprint(data)?data:'.');
+
+ data= iram->get(iram->get(start+1));
+ con->dd_printf("%06x %02x %c", iram->get(start+1), data,
+ isprint(data)?data:'.');
+ data= psw->get();
+ con->dd_printf(" PSW= 0x%02x CY=%c AC=%c OV=%c P=%c\n", data,
+ (data&bmCY)?'1':'0', (data&bmAC)?'1':'0',
+ (data&bmOV)?'1':'0', (data&bmP)?'1':'0');
+
+ print_disass(PC, con);
}
/*
- * Simulating Programmable Counter Array
*/
-int
-t_uc89c51r::do_pca(int cycles)
-{
- int ret= resGO;
- uint ccon= get_mem(MEM_SFR, CCON);
-
- if (!(ccon & bmCR))
- return(resGO);
- if (state == stIDLE &&
- (ccon & bmCIDL))
- return(resGO);
-
- switch (get_mem(MEM_SFR, CMOD) & (bmCPS1|bmCPS0))
- {
- case 0:
- ret= do_pca_counter(cycles);
- break;
- case bmCPS0:
- ret= do_pca_counter(cycles*3);
- break;
- case bmCPS1:
- ret= do_pca_counter(t0_overflows);
- t0_overflows= 0;
- break;
- case (bmCPS0|bmCPS1):
- if ((prev_p1 & bmECI) != 0 &
- (get_mem(MEM_SFR, P1) & bmECI) == 0)
- do_pca_counter(1);
- break;
- }
- return(ret);
-}
+cl_89c51r_dummy_hw::cl_89c51r_dummy_hw(class cl_uc *auc):
+ cl_hw(auc, HW_DUMMY, 0, "_89c51r_dummy")
+{}
int
-t_uc89c51r::do_pca_counter(int cycles)
+cl_89c51r_dummy_hw::init(void)
{
- while (cycles--)
+ class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
+ if (!sfr)
{
- if (/*++(MEM(MEM_SFR)[CL])*/sfr->add(CL, 1) == 0)
- {
- if (/*++(MEM(MEM_SFR)[CH])*/sfr->add(CH, 1) == 0)
- {
- /* CH,CL overflow */
- mem(MEM_SFR)->set_bit1(CCON, bmCF);
- do_pca_module(0);
- do_pca_module(1);
- do_pca_module(2);
- do_pca_module(3);
- do_pca_module(4);
- }
- }
+ fprintf(stderr, "No SFR to register %s[%d] into\n", id_string, id);
}
- return(resGO);
+ //auxr= sfr->register_hw(AUXR, this, 0);
+ register_cell(sfr, AUXR1, &auxr1, wtd_restore);
+ return(0);
}
-int
-t_uc89c51r::do_pca_module(int nr)
+void
+cl_89c51r_dummy_hw::write(class cl_memory_cell *cell, t_mem *val)
{
- uchar CCAPM[5]= {0xda, 0xdb, 0xdc, 0xdd, 0xde};
- uchar CCAPL[5]= {0xea, 0xeb, 0xec, 0xed, 0xee};
- uchar CCAPH[5]= {0xfa, 0xfb, 0xfc, 0xfd, 0xfe};
- uchar bmCEX[5]= {bmCEX0, bmCEX1, bmCEX2, bmCEX3, bmCEX4};
- uchar bmCCF[5]= {bmCCF0, bmCCF1, bmCCF2, bmCCF3, bmCCF4};
- uchar ccapm= get_mem(MEM_SFR, CCAPM[nr]);
- uint p1= get_mem(MEM_SFR, P1);
-
- if (
- ((ccapm & bmCAPP) &&
- (prev_p1 & bmCEX[nr]) == 0 &&
- (p1 & bmCEX[nr]) != 0)
- ||
- ((ccapm & bmCAPN) &&
- (prev_p1 & bmCEX[nr]) != 0 &&
- (p1 & bmCEX[nr]) == 0)
- )
- {
- /* Capture */
- //MEM(MEM_SFR)[CCAPL[nr]]= MEM(MEM_SFR)[CL];
- sfr->set(CCAPL[nr], sfr->get(CL));
- //MEM(MEM_SFR)[CCAPH[nr]]= MEM(MEM_SFR)[CH];
- sfr->set(CCAPH[nr], sfr->get(CH));
- mem(MEM_SFR)->set_bit1(CCON, bmCCF[nr]);
- }
-
- if (ccapm & bmECOM)
- {
- /* Comparator enabled */
- /*if (MEM(MEM_SFR)[CL] == MEM(MEM_SFR)[CCAPL[nr]] &&
- MEM(MEM_SFR)[CH] == MEM(MEM_SFR)[CCAPH[nr]])*/
- if (sfr->get(CL) == sfr->get(CCAPL[nr]) &&
- sfr->get(CH) == sfr->get(CCAPH[nr]))
- {
- /* Match */
- if (nr == 4 &&
- (/*MEM(MEM_SFR)[CMOD]*/sfr->get(CMOD) & bmWDTE))
- {
- reset();
- }
- mem(MEM_SFR)->set_bit1(CCON, bmCCF[nr]);
- if (ccapm & bmTOG)
- {
- /* Toggle */
- //MEM(MEM_SFR)[P1]^= bmCEX[nr];
- sfr->set(P1, sfr->get(P1) ^ bmCEX[nr]);
- }
- }
- if (ccapm & bmPWM)
- {
- /* PWM */
- if (/*MEM(MEM_SFR)[CL]*/sfr->get(CL) == 0)
- //MEM(MEM_SFR)[CCAPL[nr]]= MEM(MEM_SFR)[CCAPH[nr]];
- sfr->set(CCAPL[nr], sfr->get(CCAPH[nr]));
- if (/*MEM(MEM_SFR)[CL]*/sfr->get(CL) <
- /*MEM(MEM_SFR)[CCAPL[nr]]*/sfr->get(CCAPL[nr]))
- //MEM(MEM_SFR)[P1]&= ~(bmCEX[nr]);
- sfr->set(P1, sfr->get(P1) & ~(bmCEX[nr]));
- else
- mem(MEM_SFR)->set_bit1(P1, bmCEX[nr]);
- }
- }
-
- return(resGO);
+ if (cell == auxr1)
+ auxr1->set_bit0(0x04);
}