02111-1307, USA. */
/*@1@*/
-
// Bernhard's ToDo list:
// - implement math accelerator
// - consider ACON bits
-// - proc_write_sp (*aof_SP) / resSTACK_OV / event_at: insert this at the appropriate places
// - buy some memory to run s51 with 2*4 Meg ROM/XRAM
// strcpy (mem(MEM_ROM) ->addr_format, "0x%06x");
// strcpy (mem(MEM_XRAM)->addr_format, "0x%06x");
-
#include "ddconfig.h"
#include <stdio.h>
#include "glob.h"
#include "uc390cl.h"
#include "regs51.h"
+#include "uc390hwcl.h"
+
+
+#include "uc52cl.h"
+#include "regs51.h"
+#include "timer2cl.h"
/*
* Names of instructions
struct dis_entry disass_390f[] = {
{ 0x00, 0xff, ' ', 1, "NOP"},
- { 0x01, 0xff, 'A', 3, "AJMP %A"},
- { 0x02, 0xff, 'L', 4, "LJMP %l"},
+ { 0x01, 0xff, 'A', 3, "AJMP %A"},
+ { 0x02, 0xff, 'L', 4, "LJMP %l"},
{ 0x03, 0xff, ' ', 1, "RR A"},
{ 0x04, 0xff, ' ', 1, "INC A"},
{ 0x05, 0xff, ' ', 2, "INC %a"},
{ 0x0e, 0xff, ' ', 1, "INC R6"},
{ 0x0f, 0xff, ' ', 1, "INC R7"},
{ 0x10, 0xff, 'R', 3, "JBC %b,%R"},
- { 0x11, 0xff, 'a', 3, "ACALL %A"},
- { 0x12, 0xff, 'l', 4, "LCALL %l"},
+ { 0x11, 0xff, 'a', 3, "ACALL %A"},
+ { 0x12, 0xff, 'l', 4, "LCALL %l"},
{ 0x13, 0xff, ' ', 1, "RRC A"},
{ 0x14, 0xff, ' ', 1, "DEC A"},
{ 0x15, 0xff, ' ', 2, "DEC %a"},
{ 0x1e, 0xff, ' ', 1, "DEC R6"},
{ 0x1f, 0xff, ' ', 1, "DEC R7"},
{ 0x20, 0xff, 'R', 3, "JB %b,%R"},
- { 0x21, 0xff, 'A', 3, "AJMP %A"},
- { 0x22, 0xff, '_', 1, "RET"},
+ { 0x21, 0xff, 'A', 3, "AJMP %A"},
+ { 0x22, 0xff, '_', 1, "RET"},
{ 0x23, 0xff, ' ', 1, "RL A"},
{ 0x24, 0xff, ' ', 2, "ADD A,#%d"},
{ 0x25, 0xff, ' ', 2, "ADD A,%a"},
{ 0x2e, 0xff, ' ', 1, "ADD A,R6"},
{ 0x2f, 0xff, ' ', 1, "ADD A,R7"},
{ 0x30, 0xff, 'R', 3, "JNB %b,%R"},
- { 0x31, 0xff, 'a', 3, "ACALL %A"},
- { 0x32, 0xff, '_', 1, "RETI"},
+ { 0x31, 0xff, 'a', 3, "ACALL %A"},
+ { 0x32, 0xff, '_', 1, "RETI"},
{ 0x33, 0xff, ' ', 1, "RLC A"},
{ 0x34, 0xff, ' ', 2, "ADDC A,#%d"},
{ 0x35, 0xff, ' ', 2, "ADDC A,%a"},
{ 0x3e, 0xff, ' ', 1, "ADDC A,R6"},
{ 0x3f, 0xff, ' ', 1, "ADDC A,R7"},
{ 0x40, 0xff, 'r', 2, "JC %r"},
- { 0x41, 0xff, 'A', 3, "AJMP %A"},
+ { 0x41, 0xff, 'A', 3, "AJMP %A"},
{ 0x42, 0xff, ' ', 2, "ORL %a,A"},
{ 0x43, 0xff, ' ', 3, "ORL %a,#%D"},
{ 0x44, 0xff, ' ', 2, "ORL A,#%d"},
{ 0x4e, 0xff, ' ', 1, "ORL A,R6"},
{ 0x4f, 0xff, ' ', 1, "ORL A,R7"},
{ 0x50, 0xff, 'r', 2, "JNC %r"},
- { 0x51, 0xff, 'a', 3, "ACALL %A"},
+ { 0x51, 0xff, 'a', 3, "ACALL %A"},
{ 0x52, 0xff, ' ', 2, "ANL %a,A"},
{ 0x53, 0xff, ' ', 3, "ANL %a,#%D"},
{ 0x54, 0xff, ' ', 2, "ANL A,#%d"},
{ 0x5e, 0xff, ' ', 1, "ANL A,R6"},
{ 0x5f, 0xff, ' ', 1, "ANL A,R7"},
{ 0x60, 0xff, 'r', 2, "JZ %r"},
- { 0x61, 0xff, 'A', 3, "AJMP %A"},
+ { 0x61, 0xff, 'A', 3, "AJMP %A"},
{ 0x62, 0xff, ' ', 2, "XRL %a,A"},
{ 0x63, 0xff, ' ', 3, "XRL %a,#%D"},
{ 0x64, 0xff, ' ', 2, "XRL A,#%d"},
{ 0x6e, 0xff, ' ', 1, "XRL A,R6"},
{ 0x6f, 0xff, ' ', 1, "XRL A,R7"},
{ 0x70, 0xff, 'r', 2, "JNZ %r"},
- { 0x71, 0xff, 'a', 3, "ACALL %A"},
+ { 0x71, 0xff, 'a', 3, "ACALL %A"},
{ 0x72, 0xff, ' ', 2, "ORL C,%b"},
{ 0x73, 0xff, '_', 1, "JMP @A+DPTR"},
{ 0x74, 0xff, ' ', 2, "MOV A,#%d"},
{ 0x7e, 0xff, ' ', 2, "MOV R6,#%d"},
{ 0x7f, 0xff, ' ', 2, "MOV R7,#%d"},
{ 0x80, 0xff, 's', 2, "SJMP %r"},
- { 0x81, 0xff, 'A', 3, "AJMP %A"},
+ { 0x81, 0xff, 'A', 3, "AJMP %A"},
{ 0x82, 0xff, ' ', 2, "ANL C,%b"},
{ 0x83, 0xff, ' ', 1, "MOVC A,@A+PC"},
{ 0x84, 0xff, ' ', 1, "DIV AB"},
{ 0x8d, 0xff, ' ', 2, "MOV %a,R5"},
{ 0x8e, 0xff, ' ', 2, "MOV %a,R6"},
{ 0x8f, 0xff, ' ', 2, "MOV %a,R7"},
- { 0x90, 0xff, ' ', 4, "MOV DPTR,#%l"},
- { 0x91, 0xff, 'a', 3, "ACALL %A"},
+ { 0x90, 0xff, ' ', 4, "MOV DPTR,#%l"},
+ { 0x91, 0xff, 'a', 3, "ACALL %A"},
{ 0x92, 0xff, ' ', 2, "MOV %b,C"},
{ 0x93, 0xff, ' ', 1, "MOVC A,@A+DPTR"},
{ 0x94, 0xff, ' ', 2, "SUBB A,#%d"},
{ 0x9e, 0xff, ' ', 1, "SUBB A,R6"},
{ 0x9f, 0xff, ' ', 1, "SUBB A,R7"},
{ 0xa0, 0xff, ' ', 2, "ORL C,/%b"},
- { 0xa1, 0xff, 'A', 3, "AJMP %A"},
+ { 0xa1, 0xff, 'A', 3, "AJMP %A"},
{ 0xa2, 0xff, ' ', 2, "MOV C,%b"},
{ 0xa3, 0xff, ' ', 1, "INC DPTR"},
{ 0xa4, 0xff, ' ', 1, "MUL AB"},
{ 0xae, 0xff, ' ', 2, "MOV R6,%a"},
{ 0xaf, 0xff, ' ', 2, "MOV R7,%a"},
{ 0xb0, 0xff, ' ', 2, "ANL C,/%b"},
- { 0xb1, 0xff, 'a', 3, "ACALL %A"},
+ { 0xb1, 0xff, 'a', 3, "ACALL %A"},
{ 0xb2, 0xff, ' ', 2, "CPL %b"},
{ 0xb3, 0xff, ' ', 1, "CPL C"},
{ 0xb4, 0xff, 'R', 3, "CJNE A,#%d,%R"},
{ 0xbd, 0xff, 'R', 3, "CJNE R5,#%d,%R"},
{ 0xbe, 0xff, 'R', 3, "CJNE R6,#%d,%R"},
{ 0xbf, 0xff, 'R', 3, "CJNE R7,#%d,%R"},
- { 0xc0, 0xff, ' ', 2, "PUSH %a"},
- { 0xc1, 0xff, 'A', 3, "AJMP %A"},
+ { 0xc0, 0xff, ' ', 2, "PUSH %a"},
+ { 0xc1, 0xff, 'A', 3, "AJMP %A"},
{ 0xc2, 0xff, ' ', 2, "CLR %b"},
{ 0xc3, 0xff, ' ', 1, "CLR C"},
{ 0xc4, 0xff, ' ', 1, "SWAP A"},
{ 0xcd, 0xff, ' ', 1, "XCH A,R5"},
{ 0xce, 0xff, ' ', 1, "XCH A,R6"},
{ 0xcf, 0xff, ' ', 1, "XCH A,R7"},
- { 0xd0, 0xff, ' ', 2, "POP %a"},
- { 0xd1, 0xff, 'a', 3, "ACALL %A"},
+ { 0xd0, 0xff, ' ', 2, "POP %a"},
+ { 0xd1, 0xff, 'a', 3, "ACALL %A"},
{ 0xd2, 0xff, ' ', 2, "SETB %b"},
{ 0xd3, 0xff, ' ', 1, "SETB C"},
{ 0xd4, 0xff, ' ', 1, "DA A"},
{ 0xde, 0xff, 'r', 2, "DJNZ R6,%r"},
{ 0xdf, 0xff, 'r', 2, "DJNZ R7,%r"},
{ 0xe0, 0xff, ' ', 1, "MOVX A,@DPTR"},
- { 0xe1, 0xff, 'A', 3, "AJMP %A"},
+ { 0xe1, 0xff, 'A', 3, "AJMP %A"},
{ 0xe2, 0xff, ' ', 1, "MOVX A,@R0"},
{ 0xe3, 0xff, ' ', 1, "MOVX A,@R1"},
{ 0xe4, 0xff, ' ', 1, "CLR A"},
{ 0xee, 0xff, ' ', 1, "MOV A,R6"},
{ 0xef, 0xff, ' ', 1, "MOV A,R7"},
{ 0xf0, 0xff, ' ', 1, "MOVX @DPTR,A"},
- { 0xf1, 0xff, 'a', 3, "ACALL %A"},
+ { 0xf1, 0xff, 'a', 3, "ACALL %A"},
{ 0xf2, 0xff, ' ', 1, "MOVX @R0,A"},
{ 0xf3, 0xff, ' ', 1, "MOVX @R1,A"},
{ 0xf4, 0xff, ' ', 1, "CPL A"},
* Making an 390 CPU object
*/
-t_uc390::t_uc390 (int Itype, int Itech, class cl_sim *asim):
- t_uc52 (Itype, Itech, asim)
+cl_uc390::cl_uc390 (int Itype, int Itech, class cl_sim *asim):
+ cl_uc52 (Itype, Itech, asim)
{
if (Itype == CPU_DS390F)
{
- printf ("24-bit flat mode, warning: lots of sfr-functions not implemented!\n> ");
+ printf ("24-bit flat mode, warning: lots of sfr-functions not implemented!\n");
flat24_flag = 1;
}
+ // todo: add interrupt sources
+}
+
+void
+cl_uc390::mk_hw_elements (void)
+{
+ class cl_hw *h;
+
+ cl_uc52::mk_hw_elements();
+ hws->add (h = new cl_uc390_hw (this));
+ h->init();
}
+void
+cl_uc390::make_memories(void)
+{
+ class cl_address_space *as;
+
+ rom= as= new cl_address_space(MEM_ROM_ID, 0, 0x20000, 8);
+ as->init();
+ address_spaces->add(as);
+ iram= as= new cl_address_space(MEM_IRAM_ID, 0, 0x100, 8);
+ as->init();
+ address_spaces->add(as);
+ sfr= as= new cl_address_space(MEM_SFR_ID, 0x80, 0x80, 8);
+ as->init();
+ address_spaces->add(as);
+ xram= as= new cl_address_space(MEM_XRAM_ID, 0, 0x100000+128, 8);
+ as->init();
+ address_spaces->add(as);
+ as= new cl_address_space(MEM_IXRAM_ID, 0, 0x1000, 8);
+ as->init();
+ address_spaces->add(as);
+
+ class cl_address_decoder *ad;
+ class cl_memory_chip *chip;
+
+ chip= new cl_memory_chip("rom_chip", 0x20000, 8, 0xff);
+ chip->init();
+ memchips->add(chip);
+ ad= new cl_address_decoder(as= rom, chip, 0, 0x1ffff, 0);
+ ad->init();
+ as->decoders->add(ad);
+ ad->activate(0);
+
+ chip= new cl_memory_chip("iram_chip", 0x100, 8, 0);
+ chip->init();
+ memchips->add(chip);
+ ad= new cl_address_decoder(as= iram, chip, 0, 0xff, 0);
+ ad->init();
+ as->decoders->add(ad);
+ ad->activate(0);
+
+ chip= new cl_memory_chip("xram_chip", 0x100000+128, 8, 0);
+ chip->init();
+ memchips->add(chip);
+ ad= new cl_address_decoder(as= xram, chip, 0, 0x10007f, 0);
+ ad->init();
+ as->decoders->add(ad);
+ ad->activate(0);
+
+ chip= new cl_memory_chip("ixram_chip", 0x1000, 8);
+ chip->init();
+ memchips->add(chip);
+ ad= new cl_address_decoder(as= address_space(MEM_IXRAM_ID),
+ chip, 0, 0xfff, 0);
+ ad->init();
+ as->decoders->add(ad);
+ ad->activate(0);
+
+ chip= new cl_memory_chip("sfr_chip", 0x80, 8, 0);
+ chip->init();
+ memchips->add(chip);
+ ad= new cl_address_decoder(as= sfr, chip, 0x80, 0xff, 0);
+ ad->init();
+ as->decoders->add(ad);
+ ad->activate(0);
+
+ acc= sfr->get_cell(ACC);
+ psw= sfr->get_cell(PSW);
+}
+
+
/*
* Setting up SFR area to reset value
*/
void
-t_uc390::clear_sfr(void)
+cl_uc390::clear_sfr(void)
{
- int i;
-
- for (i = 0; i < SFR_SIZE; i++)
- sfr->set(i, 0);
- /* SFR value */
- sfr->set(0x80, 0xff); /* P4 */
- sfr->set(0x81, 0x07); /* SP */
- sfr->set(0x86, 0x04); /* DPS */
- sfr->set(0x90, 0xff); /* P1 */
- sfr->set(0x92, 0xbf); /* P4CNT */
- sfr->set(0x9b, 0xfc); /* ESP */
+ cl_uc52::clear_sfr();
+ /* SFR value */
+ sfr->write(0x80, 0xff); /* P4 */
+ sfr->write(0x81, 0x07); /* SP */
+ sfr->write(0x86, 0x04); /* DPS */
+ sfr->write(0x90, 0xff); /* P1 */
+ sfr->write(0x92, 0xbf); /* P4CNT */
+ sfr->write(0x9b, 0xfc); /* ESP */
if (flat24_flag)
- sfr->set(ACON, 0xfa); /* ACON; AM1 set: 24-bit flat */
+ sfr->/*write*/set(ACON, 0xfa); /* ACON; AM1 set: 24-bit flat */
else
- sfr->set(ACON, 0xf8); /* ACON */
- sfr->set(0xa0, 0xff); /* P2 */
- sfr->set(0xa1, 0xff); /* P5 */
- sfr->set(0xa3, 0x09); /* COC */
- sfr->set(0xb0, 0xff); /* P3 */
- sfr->set(0xb8, 0x80); /* IP */
- sfr->set(0xc5, 0x10); /* STATUS */
- sfr->set(0xc6, 0x10); /* MCON */
- sfr->set(0xc7, 0xff); /* TA */
- sfr->set(0xc9, 0xe4); /* T2MOD */
- sfr->set(0xd2, 0x2f); /* MCNT1 */
- sfr->set(0xe3, 0x09); /* C1C */
-
- prev_p1 = port_pins[1] & sfr->get(P1);
- prev_p3 = port_pins[3] & sfr->get(P3);
+ sfr->/*write*/set(ACON, 0xf8); /* ACON */
+ sfr->write(0xa0, 0xff); /* P2 */
+ sfr->write(0xa1, 0xff); /* P5 */
+ sfr->write(0xa3, 0x09); /* COC */
+ sfr->write(0xb0, 0xff); /* P3 */
+ sfr->write(0xb8, 0x80); /* IP */
+ sfr->write(0xc5, 0x10); /* STATUS */
+ sfr->write(0xc6, 0x10); /* MCON */
+ sfr->write(0xc7, 0xff); /* TA */
+ sfr->write(0xc9, 0xe4); /* T2MOD */
+ sfr->write(0xd2, 0x2f); /* MCNT1 */
+ sfr->write(0xe3, 0x09); /* C1C */
}
-t_addr
-t_uc390::get_mem_size (enum mem_class type)
-{
- switch (type)
- {
- case MEM_ROM:
- return 128*1024; // 4*1024*1024; 4 Meg possible
- case MEM_XRAM:
- return 128*1024; // 4*1024*1024; 4 Meg possible
- case MEM_IRAM:
- return 256;
- case MEM_SFR:
- return 256;
- case MEM_IXRAM:
- return 4*1024; // internal XRAM
- case MEM_TYPES:
- default:
- return 0;
- }
- return 0;
-}
-ulong
-t_uc390::read_mem(enum mem_class type, t_mem addr)
+t_mem
+cl_uc390::read_mem(char *id/*enum mem_class type*/, t_addr addr)
{
- if (type == MEM_XRAM &&
+ if (strcmp(/*type*/id,/* == */MEM_XRAM_ID)==0 &&
addr >= 0x400000 &&
(sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
{
addr -= 0x400000;
- type = MEM_IXRAM;
+ id/*type*/ = MEM_IXRAM_ID;
}
- return t_uc51::read_mem (type, addr); /* 24 bit */
+ return cl_51core::read_mem(id/*type*/, addr); /* 24 bit */
}
-ulong
-t_uc390::get_mem (enum mem_class type, t_addr addr)
+t_mem
+cl_uc390::get_mem (char *id/*enum mem_class type*/, t_addr addr)
{
- if (type == MEM_XRAM &&
+ if (strcmp(/*type*/id/* == */,MEM_XRAM_ID)==0 &&
addr >= 0x400000 &&
(sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
{
addr -= 0x400000;
- type = MEM_IXRAM;
+ /*type*/id = MEM_IXRAM_ID;
}
- return t_uc51::get_mem (type, addr);
+ return cl_51core::get_mem (/*type*/id, addr);
}
void
-t_uc390::write_mem (enum mem_class type, t_addr addr, t_mem val)
+cl_uc390::write_mem (char *id/*enum mem_class type*/, t_addr addr, t_mem val)
{
- if (type == MEM_XRAM &&
+ if (strcmp(/*type ==*/id, MEM_XRAM_ID)==0 &&
addr >= 0x400000 &&
(sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
{
addr -= 0x400000;
- type = MEM_IXRAM;
+ /*type*/id = MEM_IXRAM_ID;
}
- t_uc51::write_mem (type, addr, val);
+ cl_51core::write_mem (/*type*/id, addr, val);
}
void
-t_uc390::set_mem (enum mem_class type, t_addr addr, t_mem val)
+cl_uc390::set_mem (/*enum mem_class type*/char *id, t_addr addr, t_mem val)
{
- if (type == MEM_XRAM &&
+ if (/*type == */strcmp(id,MEM_XRAM_ID)==0 &&
addr >= 0x400000 &&
(sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
{
addr -= 0x400000;
- type = MEM_IXRAM;
+ /*type*/id = MEM_IXRAM_ID;
}
- t_uc51::set_mem (type, addr, val);
+ cl_51core::set_mem (id/*type*/, addr, val);
}
/*
*____________________________________________________________________________
*/
-int
-t_uc390::push_byte (uchar uc)
+void
+cl_uc390::push_byte (t_mem uc)
{
- int res;
+ t_addr sp;
- sfr->add (SP, 1);
+ sp = sfr->wadd (SP, 1);
if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
{
- uint sp10;
-
- if (get_mem (MEM_SFR, SP) == 0x00) /* overflow SP */
- sfr->add (ESP, 1);
- sp10 = (get_mem (MEM_SFR, ESP) & 0x3) * 256 +
- get_mem (MEM_SFR, SP);
- write_mem (MEM_IXRAM, sp10, uc);
- res = 0;
+ if (sp == 0) /* overflow SP */
+ sfr->wadd (ESP, 1);
+ sp += (sfr->read (ESP) & 0x3) * 256;
+ write_mem (MEM_IXRAM_ID, sp, uc); // fixme
}
else
{
- uchar *sp;
+ class cl_memory_cell *stck;
- sp = get_indirect (sfr->get (SP), &res);
- if (res != resGO)
- res = resSTACK_OV;
- *sp = uc;
+ stck = iram->get_cell (sp);
+ stck->write (uc);
}
- return res;
}
-uchar
-t_uc390::pop_byte (int *Pres)
+t_mem
+cl_uc390::pop_byte (void)
{
- uchar uc;
+ t_mem temp;
+ t_addr sp;
if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
{
- uint sp10;
-
- sp10 = (get_mem (MEM_SFR, ESP) & 0x3) * 256 +
- get_mem (MEM_SFR, SP);
- sfr->add (SP, -1);
- if (get_mem (MEM_SFR, SP) == 0xff) /* underflow SP */
- sfr->add (ESP, -1);
- uc = get_mem (MEM_IXRAM, sp10);
- *Pres = 0;
+ sp = sfr->read (SP);
+ sp += (sfr->read (ESP) & 0x3) * 256;
+ temp = read_mem (MEM_IXRAM_ID, sp); // fixme
+ sp = sfr->wadd (SP, -1);
+ if (sp == 0xff) /* underflow SP */
+ sfr->wadd (ESP, -1);
+ return temp;
}
else
{
- uchar *sp;
+ class cl_memory_cell *stck;
- sp = get_indirect (get_mem (MEM_SFR, SP), Pres);
- if (*Pres != resGO)
- *Pres = resSTACK_OV;
- sfr->add (SP, -1);
- uc = *sp;
+ stck = iram->get_cell (sfr->get (SP));
+ temp = stck->read();
+ sp = sfr->wadd (SP, -1);
+ return temp;
}
- return uc;
}
/*
*/
int
-t_uc390::inst_inc_dptr (uchar code)
+cl_uc390::inst_inc_dptr (uchar code)
{
ulong dptr;
uchar pl, ph, px, dps;
dps = sfr->get (DPS);
- if (dps & 1)
+ if (dps & 0x01)
{
pl = DPL1;
ph = DPH1;
px = DPX;
}
- dptr = sfr->get (ph) * 256 + sfr->get (pl);
+ dptr = sfr->read (ph) * 256 + sfr->read (pl);
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
- dptr += sfr->get (px) *256*256;
+ dptr += sfr->read (px) *256*256;
if (dps & 0x80) /* decr set */
dptr--;
else
dptr++;
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
- sfr->set (px, (dptr >> 16) & 0xff);
- sfr->set (event_at.ws = ph, (dptr >> 8) & 0xff);
- sfr->set (pl, dptr & 0xff);
+ sfr->write (px, (dptr >> 16) & 0xff);
+ sfr->write (ph, (dptr >> 8) & 0xff);
+ sfr->write (pl, dptr & 0xff);
if (dps & 0x20) /* auto-switch dptr */
- sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */
+ sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
tick (1);
return resGO;
}
*/
int
-t_uc390::inst_jmp_$a_dptr (uchar code)
+cl_uc390::inst_jmp_Sa_dptr (uchar code)
{
uchar pl, ph, px, dps;
dps = sfr->get (DPS);
- if (dps & 1)
+ if (dps & 0x01)
{
pl = DPL1;
ph = DPH1;
px = DPX;
}
- PC = (sfr->get (ph) * 256 + sfr->get (pl) +
- read_mem (MEM_SFR, ACC)) &
- (EROM_SIZE - 1);
+ PC = rom->validate_address(sfr->read (ph) * 256 + sfr->read (pl) +
+ acc->read());
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
- PC += sfr->get (px) * 256*256;
+ PC += sfr->read (px) * 256*256;
tick (1);
return resGO;
*/
int
-t_uc390::inst_mov_dptr_$data (uchar code)
+cl_uc390::inst_mov_dptr_Sdata (uchar code)
{
uchar pl, ph, px, dps;
dps = sfr->get (DPS);
- if (dps & 1)
+ if (dps & 0x01)
{
pl = DPL1;
ph = DPH1;
}
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
- sfr->set (px, fetch ());
- sfr->set (event_at.ws = ph, fetch ());
- sfr->set (pl, fetch ());
+ sfr->write (px, fetch ());
+ sfr->write (ph, fetch ());
+ sfr->write (pl, fetch ());
if (dps & 0x20) /* auto-switch dptr */
- sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */
+ sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
tick (1);
return resGO;
*/
int
-t_uc390::inst_movc_a_$a_dptr (uchar code)
+cl_uc390::inst_movc_a_Sa_dptr (uchar code)
{
uchar pl, ph, px, dps;
dps = sfr->get (DPS);
- if (dps & 1)
+ if (dps & 0x01)
{
pl = DPL1;
ph = DPH1;
}
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
- sfr->set (ACC, get_mem (MEM_ROM,
- event_at.rc =
- (sfr->get (px) * 256*256 + sfr->get (ph) * 256 + sfr->get (pl) +
- sfr->get (ACC)) & (EROM_SIZE-1)));
+ acc->write (rom->read ((sfr->read (px) * 256*256 +
+ sfr->read (ph) * 256 + sfr->read (pl) +
+ acc->read())));
else
- sfr->set (ACC, get_mem (MEM_ROM, event_at.rc =
- (sfr->get (ph) * 256 + sfr->get (pl) +
- sfr->get (ACC)) & (EROM_SIZE-1)));
+ acc->write (rom->read ((sfr->read (ph) * 256 + sfr->read (pl) +
+ acc->read())));
if (dps & 0x20) /* auto-switch dptr */
- sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */
+ sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
tick (1);
return resGO;
*/
int
-t_uc390::inst_push (uchar code)
+cl_uc390::inst_push (uchar code)
{
- uchar *addr;
- int res;
-
- addr = get_direct (fetch (), &event_at.wi, &event_at.ws);
- res = push_byte (read (addr));
+ class cl_memory_cell *cell;
+
+ cell = get_direct(fetch());
+ t_addr sp_before= sfr->get(SP);
+ t_mem data;
+ push_byte (data= cell->read());
+ class cl_stack_op *so=
+ new cl_stack_push(instPC, data, sp_before, sfr->get(SP));
+ so->init();
+ stack_write(so);
tick (1);
- return res;
+ return resGO;
}
*/
int
-t_uc390::inst_pop (uchar code)
+cl_uc390::inst_pop (uchar code)
{
- uchar *addr;
- int res;
-
- addr = get_direct (fetch (), &event_at.wi, &event_at.ws);
- *addr = pop_byte (&res);
- proc_write (addr);
+ class cl_memory_cell *cell;
+
+ t_addr sp_before= sfr->get(SP);
+ t_mem data;
+ cell = get_direct (fetch());
+ cell->write (data= pop_byte());
+ class cl_stack_op *so=
+ new cl_stack_pop(instPC, data, sp_before, sfr->get(SP));
+ so->init();
+ stack_read(so);
tick (1);
- return res;
+ return resGO;
}
*/
int
-t_uc390::inst_movx_a_$dptr (uchar code)
+cl_uc390::inst_movx_a_Sdptr (uchar code)
{
uchar pl, ph, px, dps;
dps = sfr->get (DPS);
- if (dps & 1)
+ if (dps & 0x01)
{
pl = DPL1;
ph = DPH1;
}
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
- sfr->set (event_at.ws = ACC,
- get_mem (MEM_XRAM,
- event_at.rx = sfr->get (px) * 256*256 + sfr->get (ph) * 256 + sfr->get (pl)));
+ acc->write (read_mem (MEM_XRAM_ID,
+ sfr->read (px) * 256*256 + sfr->read (ph) * 256 + sfr->read (pl)));
else
- sfr->set (event_at.ws = ACC,
- get_mem (MEM_XRAM,
- event_at.rx = sfr->get (ph) * 256 + sfr->get (pl)));
+ acc->write (read_mem (MEM_XRAM_ID,
+ sfr->read (ph) * 256 + sfr->read (pl)));
if (dps & 0x20) /* auto-switch dptr */
- sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */
+ sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
tick (1);
return resGO;
*/
int
-t_uc390::inst_movx_$dptr_a (uchar code)
+cl_uc390::inst_movx_Sdptr_a (uchar code)
{
uchar pl, ph, px, dps;
dps = sfr->get (DPS);
- if (dps & 1)
+ if (dps & 0x01)
{
pl = DPL1;
ph = DPH1;
}
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
- set_mem (MEM_XRAM,
- event_at.wx = sfr->get (px) * 256*256 + sfr->get (ph) * 256 + sfr->get (pl),
- sfr->get (event_at.rs = ACC));
+ write_mem (MEM_XRAM_ID,
+ sfr->read (px) * 256*256 + sfr->read (ph) * 256 + sfr->read (pl),
+ acc->read());
else
- set_mem (MEM_XRAM,
- event_at.wx = sfr->get (ph) * 256 + sfr->get (pl),
- sfr->get (event_at.rs = ACC));
+ write_mem (MEM_XRAM_ID,
+ sfr->read (ph) * 256 + sfr->read (pl),
+ acc->read());
if (dps & 0x20) /* auto-switch dptr */
- sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */
+ sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
tick (1);
return resGO;
*/
int
-t_uc390::inst_ajmp_addr (uchar code)
+cl_uc390::inst_ajmp_addr (uchar code)
{
uchar x, h, l;
*/
int
-t_uc390::inst_ljmp (uchar code)
+cl_uc390::inst_ljmp (uchar code)
{
uchar x, h, l;
*/
int
-t_uc390::inst_acall_addr (uchar code)
+cl_uc390::inst_acall_addr (uchar code)
{
- uchar x, h, l, *sp, *aof_SP;
- int res;
+ uchar x, h, l;
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
{
h = fetch ();
l = fetch ();
- res = push_byte ( PC & 0xff); /* push low byte */
- res = push_byte ((PC >> 8) & 0xff); /* push high byte */
- res = push_byte ((PC >> 16) & 0xff); /* push x byte */
+ push_byte ( PC & 0xff); /* push low byte */
+ push_byte ((PC >> 8) & 0xff); /* push high byte */
+ push_byte ((PC >> 16) & 0xff); /* push x byte */
PC = (PC & 0xf800) | (x * 256*256 + h * 256 + l);
}
else
{
/* stock mcs51 mode */
- h = (code >> 5) & 0x07;
- l = fetch ();
- aof_SP = &((sfr->umem8)[SP]);
-
- //MEM(MEM_SFR)[SP]++;
- (*aof_SP)++;
- proc_write_sp (*aof_SP);
- sp = get_indirect (*aof_SP/*sfr->get (SP)*/, &res);
- if (res != resGO)
- res = resSTACK_OV;
- *sp = PC & 0xff; // push low byte
-
- //MEM(MEM_SFR)[SP]++;
- (*aof_SP)++;
- proc_write_sp (*aof_SP);
- sp = get_indirect (*aof_SP/*sfr->get (SP)*/, &res);
- if (res != resGO)
- res = resSTACK_OV;
- *sp = (PC >> 8) & 0xff; // push high byte
+ class cl_memory_cell *stck;
+ t_mem sp;
- PC = (PC & 0xf800) | (h * 256 + l);
+ h = (code >> 5) & 0x07;
+ l = fetch();
+ sp = sfr->wadd (SP, 1);
+ stck = iram->get_cell (sp);
+ stck->write (PC & 0xff); // push low byte
+
+ sp = sfr->wadd (SP, 1);
+ stck = iram->get_cell (sp);
+ stck->write ((PC >> 8) & 0xff); // push high byte
+ PC = (PC & 0xf800) | (h*256 + l);
}
tick (1);
- return res;
+ return resGO;
}
/*
- * 0x12 3 24 LCALL addr
+ * 0x12 3 24 LCALL
*____________________________________________________________________________
*
*/
int
-t_uc390::inst_lcall (uchar code, uint addr)
+cl_uc390::inst_lcall (uchar code, uint addr, bool intr)
{
uchar x = 0, h = 0, l = 0;
- int res;
- if (!addr)
+ if (!intr)
{ /* this is a normal lcall */
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
x = fetch ();
}
/* else, this is interrupt processing */
- res = push_byte ( PC & 0xff); /* push low byte */
- res = push_byte ((PC >> 8) & 0xff); /* push high byte */
+ t_addr sp_before= sfr->get(SP);
+ push_byte ( PC & 0xff); /* push low byte */
+ push_byte ((PC >> 8) & 0xff); /* push high byte */
+ t_mem pushed= PC;
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
{
- res = push_byte ((PC >> 16) & 0xff); /* push x byte */
+ push_byte ((PC >> 16) & 0xff); /* push x byte */
if (addr)
PC = addr & 0xfffful; /* if interrupt: x-Byte is 0 */
else
}
else
{
+ class cl_stack_op *so;
if (addr)
- PC = addr;
+ {
+ PC = addr;
+ so= new cl_stack_intr(instPC, PC, pushed, sp_before, sfr->get(SP));
+ }
else
- PC = h * 256 + l;
+ {
+ PC = h * 256 + l;
+ so= new cl_stack_call(instPC, PC, pushed, sp_before, sfr->get(SP));
+ }
+ so->init();
+ stack_write(so);
}
- return res;
+ return resGO;
}
/*
*/
int
-t_uc390::inst_ret (uchar code)
+cl_uc390::inst_ret (uchar code)
{
uchar x = 0, h, l;
- int res;
+ t_addr sp_before= sfr->get(SP);
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
- x = pop_byte (&res);
- h = pop_byte (&res);
- l = pop_byte (&res);
+ x = pop_byte ();
+ h = pop_byte ();
+ l = pop_byte ();
tick (1);
else
PC = h * 256 + l;
- return res;
+ class cl_stack_op *so= new cl_stack_ret(instPC, PC, sp_before, sfr->get(SP));
+ so->init();
+ stack_read(so);
+ return resGO;
}
/*
*/
int
-t_uc390::inst_reti (uchar code)
+cl_uc390::inst_reti (uchar code)
{
uchar x = 0, h, l;
- int res;
+ t_addr sp_before= sfr->get(SP);
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
- x = pop_byte (&res);
- h = pop_byte (&res);
- l = pop_byte (&res);
+ x = pop_byte ();
+ h = pop_byte ();
+ l = pop_byte ();
tick (1);
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
else
PC = h * 256 + l;
- was_reti = DD_TRUE;
+ interrupt->was_reti = DD_TRUE;
class it_level *il = (class it_level *) (it_levels->top ());
if (il &&
il->level >= 0)
delete il;
}
- return res;
-}
-
-/*
- * Processing write operation to IRAM
- *
- * It starts serial transmition if address is in SFR and it is
- * SBUF. Effect on IE is also checked.
- */
-
-void
-t_uc390::proc_write(uchar *addr)
-{
- if (addr == &((sfr->umem8)[SBUF]))
- {
- s_out= sfr->get(SBUF);
- s_sending= DD_TRUE;
- s_tr_bit = 0;
- s_tr_tick= 0;
- s_tr_t1 = 0;
- }
- else if (addr == &((sfr->umem8)[IE]))
- was_reti= DD_TRUE;
- else if (addr == &((sfr->umem8)[DPS]))
- {
- *addr &= 0xe5;
- *addr |= 0x04;
- }
- else if (addr == &((sfr->umem8)[EXIF]))
- {
- }
- else if (addr == &((sfr->umem8)[P4CNT]))
- {
- ;
- }
- else if (addr == &((sfr->umem8)[ACON]))
- {
- *addr |= 0xf8;
- /* lockout: IDM1:IDM0 and SA can't be set at the same time */
- if (((sfr->umem8)[MCON] & 0xc0) == 0xc0) /* IDM1 and IDM0 set? */
- *addr &= ~0x04; /* lockout SA */
- }
- else if (addr == &((sfr->umem8)[P5CNT]))
- {
- ;
- }
- else if (addr == &((sfr->umem8)[C0C]))
- {
- ;
- }
- else if (addr == &((sfr->umem8)[PMR]))
- {
- *addr |= 0x03;
- // todo: check previous state
- if ((*addr & 0xd0) == 0x90) /* CD1:CD0 set to 10, CTM set */
- {
- ctm_ticks = ticks->ticks;
- (sfr->umem8)[EXIF] &= ~0x08; /* clear CKRDY */
- }
- else
- ctm_ticks = 0;
- }
- else if (addr == &((sfr->umem8)[MCON]))
- {
- *addr |= 0x10;
- /* lockout: IDM1:IDM0 and SA can't be set at the same time */
- if (((sfr->umem8)[ACON] & 0x04) == 0x04) /* SA set? */
- *addr &= ~0xc0; /* lockout IDM1:IDM0 */
- }
- else if (addr == &((sfr->umem8)[TA]))
- {
- if (*addr == 0x55)
- {
- timed_access_ticks = ticks->ticks;
- timed_access_state = 1;
- }
- else if (*addr == 0xaa &&
- timed_access_state == 1 &&
- timed_access_ticks == ticks->ticks + 1)
- {
- timed_access_ticks = ticks->ticks;
- timed_access_state = 2;
- }
- else
- timed_access_state = 0;
- }
- else if (addr == &((sfr->umem8)[T2MOD]))
- *addr |= 0xe0;
- else if (addr == &((sfr->umem8)[COR]))
- {
- ;
- }
- else if (addr == &((sfr->umem8)[WDCON]))
- {
- ;
- }
- else if (addr == &((sfr->umem8)[C1C]))
- {
- ;
- }
- else if (addr == &((sfr->umem8)[MCNT1]))
- *addr |= 0x0f;
-}
-
-
-/*
- * Reading IRAM or SFR, but if address points to a port, it reads
- * port pins instead of port latches
- */
-
-uchar
-t_uc390::read(uchar *addr)
-{
- //if (addr == &(MEM(MEM_SFR)[P1]))
- if (addr == &(sfr->umem8[P1]))
- return get_mem (MEM_SFR, P1) & port_pins[1];
- //if (addr == &(MEM(MEM_SFR)[P2]))
- else if (addr == &(sfr->umem8[P2]))
- return get_mem (MEM_SFR, P2) & port_pins[2];
- //if (addr == &(MEM(MEM_SFR)[P3]))
- else if (addr == &(sfr->umem8[P3]))
- return get_mem (MEM_SFR, P3) & port_pins[3];
- //if (addr == &(MEM(MEM_SFR)[P4]))
- else if (addr == &(sfr->umem8[P4]))
- return get_mem (MEM_SFR, P4) & port_pins[4];
- //if (addr == &(MEM(MEM_SFR)[P5]))
- else if (addr == &(sfr->umem8[P5]))
- return get_mem (MEM_SFR, P5) & port_pins[5];
- else if (addr == &(sfr->umem8[EXIF]))
- if (ctm_ticks &&
- ticks->ticks >= ctm_ticks + 65535)
- {
- *addr |= 0x08; /* set CKRDY */
- ctm_ticks = 0;
- }
- return *addr;
+ class cl_stack_op *so=
+ new cl_stack_iret(instPC, PC, sp_before, sfr->get(SP));
+ so->init();
+ stack_read(so);
+ return resGO;
}
*/
struct dis_entry *
-t_uc390::dis_tbl (void)
+cl_uc390::dis_tbl (void)
{
if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
return disass_390f;
}
char *
-t_uc390::disass (t_addr addr, char *sep)
+cl_uc390::disass (t_addr addr, char *sep)
{
char work[256], temp[20], c[2];
char *buf, *p, *b, *t;
t_mem code;
if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
- return t_uc51::disass (addr, sep);
- code = get_mem (MEM_ROM, addr);
+ return cl_51core::disass (addr, sep);
+ code = rom->get(addr);
p = work;
- b = dis_tbl ()[code].mnemonic;
+ b = dis_tbl()[code].mnemonic;
while (*b)
{
if (*b == '%')
// sprintf (temp, "%04lx",
// (addr & 0xf800)|
// (((code >> 5) & 0x07) * 256 +
- // get_mem (MEM_ROM, addr + 1)));
+ // rom->get (addr + 1)));
sprintf (temp, "%06lx",
- (addr & 0xf80000) |
+ (addr & 0xf80000L) |
(((code >> 5) & 0x07) * (256 * 256) +
- (get_mem (MEM_ROM, addr + 1) * 256) +
- get_mem (MEM_ROM, addr + 2)));
+ (rom->get (addr + 1) * 256) +
+ rom->get (addr + 2)));
break;
case 'l': // long address
sprintf (temp, "%06lx",
- get_mem (MEM_ROM, addr + 1) * (256*256) +
- get_mem (MEM_ROM, addr + 2) * 256 +
- get_mem (MEM_ROM, addr + 3));
- // get_mem (MEM_ROM, addr + 1) * 256 + get_mem (MEM_ROM, addr + 2));
+ rom->get (addr + 1) * (256*256L) +
+ rom->get (addr + 2) * 256 +
+ rom->get (addr + 3));
+ // rom->get (addr + 1) * 256 + rom->get (addr + 2));
break;
case 'a': // addr8 (direct address) at 2nd byte
- if (!get_name (get_mem (MEM_ROM, addr + 1), sfr_tbl (), temp))
- sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 1));
+ if (!get_name (rom->get (addr + 1), sfr_tbl (), temp))
+ sprintf (temp, "%02"_M_"x", rom->get (addr + 1));
break;
case '8': // addr8 (direct address) at 3rd byte
- if (!get_name (get_mem (MEM_ROM, addr + 2), sfr_tbl (), temp))
- sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 1));
- sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 2));
+ if (!get_name (rom->get (addr + 2), sfr_tbl (), temp))
+ sprintf (temp, "%02"_M_"x", rom->get (addr + 2));
break;
case 'b': // bitaddr at 2nd byte
- if (get_name (get_mem (MEM_ROM, addr + 1), bit_tbl (), temp))
- break;
- if (get_name (get_bitidx (get_mem (MEM_ROM, addr + 1)),
- sfr_tbl (), temp))
- {
- strcat (temp, ".");
- sprintf (c, "%1ld", get_mem (MEM_ROM, addr + 1) & 0x07);
- strcat (temp, c);
+ {
+ t_addr ba = rom->get (addr+1);
+ if (get_name (ba, bit_tbl(), temp))
break;
- }
- sprintf (temp, "%02x.%ld",
- get_bitidx (get_mem (MEM_ROM, addr + 1)),
- get_mem (MEM_ROM, addr + 1) & 0x07);
- break;
+ if (get_name ((ba<128) ? ((ba/8)+32) : (ba&0xf8), sfr_tbl(), temp))
+ {
+ strcat (temp, ".");
+ sprintf (c, "%1"_M_"d", ba & 0x07);
+ strcat (temp, c);
+ break;
+ }
+ sprintf (temp, "%02x.%"_M_"d", (ba<128) ? ((ba/8)+32) : (ba&0xf8),
+ ba & 0x07);
+ break;
+ }
case 'r': // rel8 address at 2nd byte
- sprintf (temp, "%04lx",
- addr + 2 + (signed char) (get_mem (MEM_ROM, addr + 1)));
+ sprintf (temp, "%04"_A_"x",
+ t_addr (addr + 2 + (signed char) (rom->get (addr + 1))));
break;
case 'R': // rel8 address at 3rd byte
- sprintf (temp, "%04lx",
- addr + 3 + (signed char) (get_mem (MEM_ROM, addr + 2)));
+ sprintf (temp, "%04"_A_"x",
+ t_addr (addr + 3 + (signed char) (rom->get (addr + 2))));
break;
case 'd': // data8 at 2nd byte
- sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 1));
+ sprintf (temp, "%02"_M_"x", rom->get (addr + 1));
break;
case 'D': // data8 at 3rd byte
- sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 2));
+ sprintf (temp, "%02"_M_"x", rom->get (addr + 2));
break;
default:
strcpy (temp, "?");
}
void
-t_uc390::print_regs (class cl_console *con)
+cl_uc390::print_regs (class cl_console_base *con)
{
t_addr start;
- uchar data;
+ t_mem data;
if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
{
- t_uc51::print_regs (con);
+ cl_51core::print_regs (con);
return;
}
start = sfr->get (PSW) & 0x18;
iram->dump (start, start + 7, 8, con);
start = sfr->get (PSW) & 0x18;
data = iram->get (iram->get (start));
- con->printf ("%06x %02x %c",
- iram->get (start), data, isprint (data) ? data : '.');
- con->printf (" ACC= 0x%02x %3d %c B= 0x%02x",
- sfr->get (ACC), sfr->get (ACC),
- isprint (sfr->get (ACC)) ? (sfr->get (ACC)) : '.', sfr->get (B));
+ con->dd_printf("%06x %02x %c",
+ iram->get (start), data, isprint (data) ? data : '.');
+ con->dd_printf(" ACC= 0x%02x %3d %c B= 0x%02x",
+ sfr->get (ACC), sfr->get (ACC),
+ isprint (sfr->get (ACC)) ?
+ (sfr->get (ACC)) : '.', sfr->get (B));
eram2xram ();
- data = get_mem (MEM_XRAM,
+ data = get_mem (MEM_XRAM_ID,
sfr->get (DPX) * 256*256 + sfr->get (DPH) * 256 + sfr->get (DPL));
- con->printf (" DPTR= 0x%02x%02x%02x @DPTR= 0x%02x %3d %c\n",
- sfr->get (DPX), sfr->get (DPH), sfr->get (DPL),
- data, data, isprint (data) ? data : '.');
+ con->dd_printf (" DPTR= 0x%02x%02x%02x @DPTR= 0x%02x %3d %c\n",
+ sfr->get (DPX), sfr->get (DPH), sfr->get (DPL),
+ data, data, isprint (data) ? data : '.');
data = iram->get (iram->get (start + 1));
- con->printf ("%06x %02x %c", iram->get (start + 1), data,
- isprint (data) ? data : '.');
+ con->dd_printf ("%06x %02x %c", iram->get (start + 1), data,
+ isprint (data) ? data : '.');
data= sfr->get (PSW);
- con->printf (" PSW= 0x%02x CY=%c AC=%c OV=%c P=%c ",
- data,
- (data & bmCY) ? '1' : '0', (data & bmAC) ? '1' : '0',
- (data & bmOV) ? '1' : '0', (data & bmP ) ? '1' : '0'
- );
+ con->dd_printf (" PSW= 0x%02x CY=%c AC=%c OV=%c P=%c ",
+ data,
+ (data & bmCY) ? '1' : '0', (data & bmAC) ? '1' : '0',
+ (data & bmOV) ? '1' : '0', (data & bmP ) ? '1' : '0'
+ );
/* show stack pointer */
if (sfr->get (ACON) & 0x04)
/* SA: 10 bit stack */
- con->printf ("SP10 0x%03x %3d\n",
- (sfr->get (ESP) & 3) * 256 + sfr->get (SP),
- get_mem (MEM_IXRAM, (sfr->get (ESP) & 3) * 256 + sfr->get (SP))
- );
+ con->dd_printf ("SP10 0x%03x %3d\n",
+ (sfr->get (ESP) & 3) * 256 + sfr->get (SP),
+ get_mem (MEM_IXRAM_ID, (sfr->get (ESP) & 3) * 256 + sfr->get (SP))
+ );
else
- con->printf ("SP 0x%02x %3d\n",
- sfr->get (SP),
- iram->get (sfr->get (SP))
- );
+ con->dd_printf ("SP 0x%02x %3d\n",
+ sfr->get (SP),
+ iram->get (sfr->get (SP))
+ );
print_disass (PC, con);
}
+
+
/* End of s51.src/uc390.cc */
projects / fw / sdcc / blobdiff