cl_uc(asim)
{
type= CPU_AVR;
+ sleep_executed= 0;
}
int
case MEM_IRAM: return(0x10000);
default: return(0);
}
- return(cl_uc::get_mem_size(type));
+ //return(0);
+ //return(cl_uc::get_mem_size(type));
}
int
}
char *
-cl_avr::disass(uint addr, char *sep)
+cl_avr::disass(t_addr addr, char *sep)
{
char work[256], temp[20];
char *buf, *p, *b, *t;
int k= code&0xfff;
if (code&0x800)
k|= -4096;
- sprintf(temp, "0x%06lx",
- (k+1+(signed int)addr) % rom->size);
+ sprintf(temp, "0x%06"_A_"x",
+ t_addr((k+1+(signed int)addr) % rom->size));
break;
}
default:
return(buf);
}
-void
-cl_avr::print_disass(uint addr, class cl_console *con)
-{
- char *dis;
- class cl_brk *b;
- int i;
-
- b = fbrk_at(addr);
- dis= disass(addr, NULL);
- if (b)
- con->printf("%c", (b->perm == brkFIX)?'F':'D');
- else
- con->printf(" ");
- con->printf("%c %06x %04x",
- inst_at(addr)?' ':'*',
- addr, get_mem(MEM_ROM, addr));
- for (i= 1; i < inst_length(get_mem(MEM_ROM, addr)); i++)
- con->printf(" %04x", get_mem(MEM_ROM, addr+i));
- while (i < 2)
- {
- con->printf(" ");
- i++;
- }
- con->printf(" %s\n", dis);
- free(dis);
-}
void
cl_avr::print_regs(class cl_console *con)
ram->dump(0, 31, 16, con);
- con->printf("ITHSVNZC SREG= 0x%02x %3d %c\n",
- sreg, sreg, isprint(sreg)?sreg:'.');
- con->printf("%c%c%c%c%c%c%c%c ",
- (sreg&BIT_I)?'1':'0',
- (sreg&BIT_T)?'1':'0',
- (sreg&BIT_H)?'1':'0',
- (sreg&BIT_S)?'1':'0',
- (sreg&BIT_V)?'1':'0',
- (sreg&BIT_N)?'1':'0',
- (sreg&BIT_Z)?'1':'0',
- (sreg&BIT_C)?'1':'0');
- con->printf("SP = 0x%06x\n",
- ram->get(SPH)*256+ram->get(SPL));
+ con->dd_printf("ITHSVNZC SREG= 0x%02x %3d %c\n",
+ sreg, sreg, isprint(sreg)?sreg:'.');
+ con->dd_printf("%c%c%c%c%c%c%c%c ",
+ (sreg&BIT_I)?'1':'0',
+ (sreg&BIT_T)?'1':'0',
+ (sreg&BIT_H)?'1':'0',
+ (sreg&BIT_S)?'1':'0',
+ (sreg&BIT_V)?'1':'0',
+ (sreg&BIT_N)?'1':'0',
+ (sreg&BIT_Z)?'1':'0',
+ (sreg&BIT_C)?'1':'0');
+ con->dd_printf("SP = 0x%06x\n", ram->get(SPH)*256+ram->get(SPL));
x= ram->get(XH)*256 + ram->get(XL);
data= ram->get(x);
- con->printf("X= 0x%04x [X]= 0x%02x %3d %c ", x,
- data, data, isprint(data)?data:'.');
+ con->dd_printf("X= 0x%04x [X]= 0x%02x %3d %c ", x,
+ data, data, isprint(data)?data:'.');
y= ram->get(YH)*256 + ram->get(YL);
data= ram->get(y);
- con->printf("Y= 0x%04x [Y]= 0x%02x %3d %c ", y,
- data, data, isprint(data)?data:'.');
+ con->dd_printf("Y= 0x%04x [Y]= 0x%02x %3d %c ", y,
+ data, data, isprint(data)?data:'.');
z= ram->get(ZH)*256 + ram->get(ZL);
data= ram->get(z);
- con->printf("Z= 0x%04x [Z]= 0x%02x %3d %c\n", z,
- data, data, isprint(data)?data:'.');
+ con->dd_printf("Z= 0x%04x [Z]= 0x%02x %3d %c\n", z,
+ data, data, isprint(data)?data:'.');
print_disass(PC, con);
}
return(ijmp(code));
if ((code & 0xff00) == 0x9600)
return(adiw_Rdl_K(code));
+ if ((code & 0xff00) == 0x9700)
+ return(sbiw_Rdl_K(code));
switch (code & 0xfc00)
{
case 0x9000:
}
+/*
+ */
+
+int
+cl_avr::push_data(t_mem data)
+{
+ t_addr sp;
+ t_mem spl, sph;
+
+ spl= ram->read(SPL);
+ sph= ram->read(SPH);
+ sp= 0xffff & (256*sph + spl);
+ data= ram->write(sp, data);
+ sp= 0xffff & (sp-1);
+ spl= sp & 0xff;
+ sph= (sp>>8) & 0xff;
+ ram->write(SPL, spl);
+ ram->write(SPH, sph);
+ return(resGO);
+}
+
+int
+cl_avr::push_addr(t_addr addr)
+{
+ t_addr sp;
+ t_mem spl, sph, al, ah;
+
+ spl= ram->read(SPL);
+ sph= ram->read(SPH);
+ sp= 0xffff & (256*sph + spl);
+ al= addr & 0xff;
+ ah= (addr>>8) & 0xff;
+ ram->write(sp, ah);
+ sp= 0xffff & (sp-1);
+ ram->write(sp, al);
+ sp= 0xffff & (sp-1);
+ spl= sp & 0xff;
+ sph= (sp>>8) & 0xff;
+ ram->write(SPL, spl);
+ ram->write(SPH, sph);
+ return(resGO);
+}
+
+int
+cl_avr::pop_data(t_mem *data)
+{
+ t_addr sp;
+ t_mem spl, sph;
+
+ spl= ram->read(SPL);
+ sph= ram->read(SPH);
+ sp= 256*sph + spl;
+ sp= 0xffff & (sp+1);
+ *data= ram->read(sp);
+ spl= sp & 0xff;
+ sph= (sp>>8) & 0xff;
+ ram->write(SPL, spl);
+ ram->write(SPH, sph);
+
+ return(resGO);
+}
+
+int
+cl_avr::pop_addr(t_addr *addr)
+{
+ t_addr sp;
+ t_mem spl, sph, al, ah;
+
+ spl= ram->read(SPL);
+ sph= ram->read(SPH);
+ sp= 256*sph + spl;
+ sp= 0xffff & (sp+1);
+ al= ram->read(sp);
+ sp= 0xffff & (sp+1);
+ ah= ram->read(sp);
+ *addr= ah*256 + al;
+ spl= sp & 0xff;
+ sph= (sp>>8) & 0xff;
+ ram->write(SPL, spl);
+ ram->write(SPH, sph);
+
+ return(resGO);
+}
+
+
/*
* Set Z, N, V, S bits of SREG after logic instructions and some others
*/