return d_u2->mac_addr();
}
+std::string
+usrp2_base::interface_name() const
+{
+ return d_u2->interface_name();
+}
+
bool
usrp2_base::fpga_master_clock_freq(long *freq) const
{
return d_u2->fpga_master_clock_freq(freq);
}
+bool
+usrp2_base::config_mimo(int flags)
+{
+ return d_u2->config_mimo(flags);
+}
+
bool
usrp2_base::sync_to_pps()
{
return d_u2->sync_to_pps();
}
-std::vector<uint8_t>
-usrp2_base::peek(uint32_t addr, uint32_t len)
+bool
+usrp2_base::sync_every_pps(bool enable)
+{
+ return d_u2->sync_every_pps(enable);
+}
+
+std::vector<uint32_t>
+usrp2_base::peek32(uint32_t addr, uint32_t words)
+{
+ return d_u2->peek32(addr, words);
+}
+
+bool
+usrp2_base::poke32(uint32_t addr, const std::vector<uint32_t> &data)
{
- return d_u2->peek(addr, len);
+ return d_u2->poke32(addr, data);
}
bool