Merged r9834:9855 from jcorgan/u2-wip into trunk. Catches up gr-usrp2 with the lates...

[debian/gnuradio] / gr-usrp2 / src / usrp2.i

diff --git a/gr-usrp2/src/usrp2.i b/gr-usrp2/src/usrp2.i
index 9f82c4cdeb0f6ffd211636213c5a0831e9b083cc..7c75287cb6b269a4df44791b6c853525dd138450 100644 (file)
--- a/gr-usrp2/src/usrp2.i
+++ b/gr-usrp2/src/usrp2.i
@@ -46,6 +46,8 @@ public:
   ~usrp2_base();
 
   std::string mac_addr() const;
+  %rename(_real_fpga_master_clock_freq) fpga_master_clock_freq;
+  bool fpga_master_clock_freq(long *freq);
 };
 
 // ----------------------------------------------------------------
@@ -62,6 +64,19 @@ public:
   %rename(_real_set_center_freq) set_center_freq;
   bool set_center_freq(double frequency, usrp2::tune_result *r);
   bool set_decim(int decimation_factor);
+  bool set_scale_iq(int scale_i, int scale_q);
+  int decim();
+  %rename(_real_adc_rate) adc_rate;
+  bool adc_rate(long *rate);
+  double gain_min();
+  double gain_max();
+  double gain_db_per_step();
+  double freq_min();
+  double freq_max();
+  %rename(_real_daughterboard_id) daughterboard_id;
+  bool daughterboard_id(int *dbid);
+  unsigned int overruns();
+  unsigned int missing();
 };
 
 // ----------------------------------------------------------------
@@ -114,6 +129,17 @@ public:
   %rename(_real_set_center_freq) set_center_freq;
   bool set_center_freq(double frequency, usrp2::tune_result *r);
   bool set_interp(int interp_factor);
+  bool set_scale_iq(int scale_i, int scale_q);
+  int interp();
+  %rename(_real_dac_rate) dac_rate;
+  bool dac_rate(long *rate);
+  double gain_min();
+  double gain_max();
+  double gain_db_per_step();
+  double freq_min();
+  double freq_max();
+  %rename(_real_daughterboard_id) daughterboard_id;
+  bool daughterboard_id(int *dbid);
 };
 
 // ----------------------------------------------------------------
@@ -154,6 +180,23 @@ public:
 
 // ----------------------------------------------------------------
 
+// some utility functions to allow Python to deal with pointers
+%{
+  long *make_long_ptr() { return (long *)malloc(sizeof(long)); }
+  long deref_long_ptr(long *l) { return *l; }
+  void free_long_ptr(long *l) { free(l); }
+  int *make_int_ptr() { return (int *)malloc(sizeof(int)); }
+  int deref_int_ptr(int *l) { return *l; }
+  void free_int_ptr(int *l) { free(l); }
+%}
+
+long *make_long_ptr();
+long deref_long_ptr(long *l);
+void free_long_ptr(long *l);
+int *make_int_ptr();
+int deref_int_ptr(int *l);
+void free_int_ptr(int *l);
+
 // create a more pythonic interface
 %pythoncode %{
 
@@ -165,8 +208,86 @@ def __set_center_freq(self, freq):
   else:
     return None
 
+def __fpga_master_clock_freq(self):
+  f = make_long_ptr();
+  r = self._real_fpga_master_clock_freq(f)
+  if r:
+    result = deref_long_ptr(f)
+  else:
+    result = None
+  free_long_ptr(f)
+  return result
+
+def __adc_rate(self):
+  rate = make_long_ptr();
+  r = self._real_adc_rate(rate)
+  if r:
+    result = deref_long_ptr(rate)
+  else:
+    result = None
+  free_long_ptr(rate)
+  return result
+
+def __dac_rate(self):
+  rate = make_long_ptr();
+  r = self._real_dac_rate(rate)
+  if r:
+    result = deref_long_ptr(rate)
+  else:
+    result = None
+  free_long_ptr(rate)
+  return result
+
+def __gain_range(self):
+  return [self.gain_min(),
+          self.gain_max(),
+          self.gain_db_per_step()]
+
+# NOTE: USRP1 uses a length three tuple here (3rd value is 'freq step'),
+#       but it's not really useful.  We let an index error happen here
+#       to identify code using it.
+def __freq_range(self):
+  return [self.freq_min(),
+          self.freq_max()]
+
+def __daughterboard_id(self):
+  dbid = make_int_ptr();
+  r = self._real_daughterboard_id(dbid)
+  if r:
+    result = deref_int_ptr(dbid)
+  else:
+    result = None
+  free_int_ptr(dbid)
+  return result
+
 usrp2_source_32fc_sptr.set_center_freq = __set_center_freq
 usrp2_source_16sc_sptr.set_center_freq = __set_center_freq
 usrp2_sink_32fc_sptr.set_center_freq = __set_center_freq
 usrp2_sink_16sc_sptr.set_center_freq = __set_center_freq
+
+usrp2_source_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
+usrp2_source_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
+usrp2_sink_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
+usrp2_sink_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
+
+usrp2_source_32fc_sptr.adc_rate = __adc_rate
+usrp2_source_16sc_sptr.adc_rate = __adc_rate
+usrp2_sink_32fc_sptr.dac_rate = __dac_rate
+usrp2_sink_16sc_sptr.dac_rate = __dac_rate
+
+usrp2_source_32fc_sptr.gain_range = __gain_range
+usrp2_source_16sc_sptr.gain_range = __gain_range
+usrp2_sink_32fc_sptr.gain_range = __gain_range
+usrp2_sink_16sc_sptr.gain_range = __gain_range
+
+usrp2_source_32fc_sptr.freq_range = __freq_range
+usrp2_source_16sc_sptr.freq_range = __freq_range
+usrp2_sink_32fc_sptr.freq_range = __freq_range
+usrp2_sink_16sc_sptr.freq_range = __freq_range
+
+usrp2_source_32fc_sptr.daughterboard_id = __daughterboard_id
+usrp2_source_16sc_sptr.daughterboard_id = __daughterboard_id
+usrp2_sink_32fc_sptr.daughterboard_id = __daughterboard_id
+usrp2_sink_16sc_sptr.daughterboard_id = __daughterboard_id
+
 %}