new experimental daughterboards with other tuners

[debian/gnuradio] / gr-usrp / src / db_base.py

diff --git a/gr-usrp/src/db_base.py b/gr-usrp/src/db_base.py
index 4f4db38f4b07a35794c0c924afb8284156fc7b59..947f815592c952ccb63d71754fefb40d7203a5f0 100644 (file)
--- a/gr-usrp/src/db_base.py
+++ b/gr-usrp/src/db_base.py
@@ -1,11 +1,11 @@
 #
-# Copyright 2005,2006 Free Software Foundation, Inc.
+# Copyright 2005,2006,2007 Free Software Foundation, Inc.
 # 
 # This file is part of GNU Radio
 # 
 # GNU Radio is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
+# the Free Software Foundation; either version 3, or (at your option)
 # any later version.
 # 
 # GNU Radio is distributed in the hope that it will be useful,
@@ -15,13 +15,13 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with GNU Radio; see the file COPYING.  If not, write to
-# the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-# Boston, MA 02111-1307, USA.
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
 # 
 
-import usrp_prims
 import weakref
-from usrp_fpga_regs import *
+from usrpm import usrp_prims
+from usrpm.usrp_fpga_regs import *
 
 class db_base(object):
     """
@@ -51,14 +51,8 @@ class db_base(object):
             self._tx = False
             self._slot = which * 2 + 1
 
-        FR_TX_A_REFCLK = 40
-        FR_RX_A_REFCLK = 41
-        FR_TX_B_REFCLK = 42
-        FR_RX_B_REFCLK = 43
-
         self._refclk_reg = (FR_TX_A_REFCLK,FR_RX_A_REFCLK,FR_TX_B_REFCLK,FR_RX_B_REFCLK)[self._slot]
 
-
     def dbid(self):
         return self._u.daughterboard_id(self._which)
 
@@ -88,7 +82,6 @@ class db_base(object):
     # Bit 7  -- 1 turns on refclk, 0 allows IO use
     # Bits 6:0 Divider value
     #
-    # FIXME get these from the fpga_regs_standard.h
     
     def _refclk_freq(self):
         return self._u.fpga_master_clock_freq()/self._refclk_divisor()
@@ -154,6 +147,20 @@ class db_base(object):
         """
         return self._u._write_fpga_reg(FR_ATR_RXVAL_0 + 3 * self._slot, v)
 
+    def set_atr_tx_delay(self, v):
+       """
+       Set Auto T/R delay (in clock ticks) from when Tx fifo gets data to 
+       when T/R switches.
+       """
+       return self._u._write_fpga_reg(FR_ATR_TX_DELAY, v)
+       
+    def set_atr_rx_delay(self, v):
+       """
+       Set Auto T/R delay (in clock ticks) from when Tx fifo goes empty to 
+       when T/R switches.
+       """
+       return self._u._write_fpga_reg(FR_ATR_RX_DELAY, v)
+       
     # derived classes should override the following methods
 
     def freq_range(self):
@@ -207,7 +214,8 @@ class db_base(object):
 
     def i_and_q_swapped(self):
         """
-        Return True if this is a quadrature device and ADC 0 is Q.
+        Return True if this is a quadrature device and (for RX) ADC 0 is Q
+        or (for TX) DAC 0 is Q
         """
         return False
 
@@ -232,3 +240,25 @@ class db_base(object):
         """
         pass
 
+    def set_lo_offset(self, offset):
+       """
+       Set how much LO is offset from requested frequency
+       
+       Should be overriden by daughterboards that care.
+       """
+       pass
+       
+    def lo_offset(self, offset):
+       """
+       Get how much LO is offset from requested frequency
+
+       Should be overriden by daughterboards that care.
+       """
+       return 0.0
+
+    def select_rx_antenna(self, which_antenna):
+       """
+       Specify which antenna port to use for reception.
+       Should be overriden by daughterboards that care.
+       """
+       pass