build: update version number to 3.3.1

[debian/gnuradio] / gr-sounder / src / fpga / top / usrp_sounder.qsf

diff --git a/gr-sounder/src/fpga/top/usrp_sounder.qsf b/gr-sounder/src/fpga/top/usrp_sounder.qsf
old mode 100755 (executable)
new mode 100644 (file)
index 5ff5258..4d60f5f
--- a/gr-sounder/src/fpga/top/usrp_sounder.qsf
+++ b/gr-sounder/src/fpga/top/usrp_sounder.qsf
@@ -236,7 +236,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF\r
 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF\r
 set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF\r
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL\r
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA\r
 set_global_assignment -name INC_PLC_MODE OFF\r
 set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF\r
 set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]\r
@@ -368,13 +368,15 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
 set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top\r
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\r
 \r
-set_global_assignment -name VERILOG_FILE ../lib/strobe.v\r
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF\r
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE REALISTIC\r
 set_global_assignment -name VERILOG_FILE ../lib/lfsr_constants.v\r
 set_global_assignment -name VERILOG_FILE ../lib/lfsr.v\r
 set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v\r
 set_global_assignment -name VERILOG_FILE ../lib/dacpll.v\r
 set_global_assignment -name VERILOG_FILE ../lib/sounder_rx.v\r
 set_global_assignment -name VERILOG_FILE ../lib/sounder_tx.v\r
+set_global_assignment -name VERILOG_FILE ../lib/sounder_ctrl.v\r
 set_global_assignment -name VERILOG_FILE ../lib/sounder.v\r
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v\r
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/sign_extend.v\r
@@ -390,4 +392,5 @@ set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_co
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v\r
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v\r
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v\r
-set_global_assignment -name VERILOG_FILE usrp_sounder.v
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE usrp_sounder.v\r
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
\ No newline at end of file