input ena_i;
input strobe_i;
- input [15:0] tx_i_i;
- input [15:0] tx_q_i;
+ input [13:0] tx_i_i;
+ input [13:0] tx_q_i;
- output [15:0] tx_data_o;
+ output [13:0] tx_data_o;
output tx_sync_o;
`ifdef TX_RATE_MAX
wire clk128;
reg clk64_d;
- reg [15:0] tx_data_o;
+ reg [13:0] tx_data_o;
// Create a 128 MHz clock
dacpll pll128(.areset(rst_i),.inclk0(clk_i),.c0(clk128));