switch source package format to 3.0 quilt

[debian/gnuradio] / gr-radar-mono / src / fpga / lib / radar_control.v

diff --git a/gr-radar-mono/src/fpga/lib/radar_control.v b/gr-radar-mono/src/fpga/lib/radar_control.v
index 4f88645bb2da6521aa82ed41042bd589e9876039..05b78198d8510753d53fb4f52429d3b9d7765e2b 100644 (file)
--- a/gr-radar-mono/src/fpga/lib/radar_control.v
+++ b/gr-radar-mono/src/fpga/lib/radar_control.v
@@ -21,10 +21,10 @@
 
 `include "../lib/radar_config.vh"
 
-module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
-                    reset_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
-                    ampl_o,fstart_o,fincr_o);
-
+module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
+                    tx_side_o,dbg_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
+                    ampl_o,fstart_o,fincr_o,pulse_num_o,io_tx_ena_o);
+   
    // System interface
    input         clk_i;                // Master clock @ 64 MHz
    input  [6:0]  saddr_i;      // Configuration bus address
@@ -33,27 +33,40 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
 
    // Control and configuration outputs
    output       reset_o;
+   output        tx_side_o;
+   output        dbg_o;
    output        tx_strobe_o;
    output        tx_ctrl_o;
    output        rx_ctrl_o;
    output [15:0] ampl_o;
    output [31:0] fstart_o;
    output [31:0] fincr_o;
+   output [15:0] pulse_num_o;
+   output        io_tx_ena_o;
    
    // Internal configuration
    wire         lp_ena;
-   wire         dr_ena;
    wire         md_ena;
+   wire         dr_ena;
    wire   [1:0]  chirps;
    wire   [15:0] t_on;
    wire   [15:0] t_sw;
    wire   [15:0] t_look;
    wire   [31:0] t_idle;
-
+   wire   [31:0] atrdel;
+   
    // Configuration from host
+   wire [31:0]          mode;
    setting_reg #(`FR_RADAR_MODE)   sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
-                                          .out({chirps,md_ena,dr_ena,lp_ena,reset_o}));
-                                    
+                                          .out(mode));
+   assign reset_o   = mode[0];
+   assign tx_side_o = mode[1];
+   assign lp_ena    = mode[2];
+   assign md_ena    = mode[3];
+   assign dr_ena    = mode[4];
+   assign chirps    = mode[6:5];
+   assign dbg_o     = mode[7];
+   
    setting_reg #(`FR_RADAR_TON)    sr_ton(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
                                          .out(t_on));
    
@@ -75,6 +88,9 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
    setting_reg #(`FR_RADAR_FINCR)  sr_fincr(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
                                            .out(fincr_o));
 
+   setting_reg #(`FR_RADAR_ATRDEL)  sr_atrdel(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+                                           .out(atrdel));
+   
    // Pulse state machine
    `define ST_ON   4'b0001
    `define ST_SW   4'b0010
@@ -83,12 +99,14 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
 
    reg [3:0]  state;
    reg [31:0] count;
-
+   reg [15:0] pulse_num_o;
+   
    always @(posedge clk_i)
      if (reset_o)
        begin
          state <= `ST_ON;
          count <= 32'b0;
+         pulse_num_o <= 16'b0;
        end
      else
        case (state)
@@ -97,6 +115,7 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
             begin
                state <= `ST_SW;
                count <= 32'b0;
+               pulse_num_o <= pulse_num_o + 16'b1;
             end
           else
             count <= count + 32'b1;
@@ -108,7 +127,7 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
                count <= 32'b0;
             end
           else
-            count <= count + 24'b1;
+            count <= count + 32'b1;
 
         `ST_LOOK:
           if (count == {16'b0,t_look})
@@ -123,7 +142,7 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
           if (count == t_idle)
             begin
                state <= `ST_ON;
-               count <= 24'b0;
+               count <= 32'b0;
             end
           else
             count <= count + 32'b1;
@@ -138,5 +157,10 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
    assign tx_strobe_o = count[0]; // Drive DAC inputs at 32 MHz
    assign tx_ctrl_o = (state == `ST_ON);
    assign rx_ctrl_o = (state == `ST_LOOK);
+
+   // Create delayed version of tx_ctrl_o to drive mixers and TX/RX switch
+   atr_delay atr_delay(.clk_i(clk_i),.rst_i(reset_o),.ena_i(1'b1),.tx_empty_i(!tx_ctrl_o),
+                      .tx_delay_i(atrdel[27:16]),.rx_delay_i(atrdel[11:0]),
+                      .atr_tx_o(io_tx_ena_o));
    
 endmodule // radar_control