--- /dev/null
+// megafunction wizard: %FIFO%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: scfifo \r
+\r
+// ============================================================\r
+// File Name: fifo32_2k.v\r
+// Megafunction Name(s):\r
+// scfifo\r
+//\r
+// Simulation Library Files(s):\r
+// altera_mf\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2007 Altera Corporation\r
+//Your use of Altera Corporation's design tools, logic functions \r
+//and other software and tools, and its AMPP partner logic \r
+//functions, and any output files from any of the foregoing \r
+//(including device programming or simulation files), and any \r
+//associated documentation or information are expressly subject \r
+//to the terms and conditions of the Altera Program License \r
+//Subscription Agreement, Altera MegaCore Function License \r
+//Agreement, or other applicable license agreement, including, \r
+//without limitation, that your use is for the sole purpose of \r
+//programming logic devices manufactured by Altera and sold by \r
+//Altera or its authorized distributors. Please refer to the \r
+//applicable agreement for further details.\r
+\r
+\r
+// synopsys translate_off\r
+`timescale 1 ps / 1 ps\r
+// synopsys translate_on\r
+module fifo32_2k (\r
+ clock,\r
+ data,\r
+ rdreq,\r
+ sclr,\r
+ wrreq,\r
+ empty,\r
+ q);\r
+\r
+ input clock;\r
+ input [31:0] data;\r
+ input rdreq;\r
+ input sclr;\r
+ input wrreq;\r
+ output empty;\r
+ output [31:0] q;\r
+\r
+ wire sub_wire0;\r
+ wire [31:0] sub_wire1;\r
+ wire empty = sub_wire0;\r
+ wire [31:0] q = sub_wire1[31:0];\r
+\r
+ scfifo scfifo_component (\r
+ .rdreq (rdreq),\r
+ .sclr (sclr),\r
+ .clock (clock),\r
+ .wrreq (wrreq),\r
+ .data (data),\r
+ .empty (sub_wire0),\r
+ .q (sub_wire1)\r
+ // synopsys translate_off\r
+ ,\r
+ .aclr (),\r
+ .almost_empty (),\r
+ .almost_full (),\r
+ .full (),\r
+ .usedw ()\r
+ // synopsys translate_on\r
+ );\r
+ defparam\r
+ scfifo_component.add_ram_output_register = "OFF",\r
+ scfifo_component.intended_device_family = "Cyclone",\r
+ scfifo_component.lpm_numwords = 2048,\r
+ scfifo_component.lpm_showahead = "OFF",\r
+ scfifo_component.lpm_type = "scfifo",\r
+ scfifo_component.lpm_width = 32,\r
+ scfifo_component.lpm_widthu = 11,\r
+ scfifo_component.overflow_checking = "OFF",\r
+ scfifo_component.underflow_checking = "OFF",\r
+ scfifo_component.use_eab = "ON";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"\r
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"\r
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"\r
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"\r
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"\r
+// Retrieval info: PRIVATE: Clock NUMERIC "0"\r
+// Retrieval info: PRIVATE: Depth NUMERIC "2048"\r
+// Retrieval info: PRIVATE: Empty NUMERIC "1"\r
+// Retrieval info: PRIVATE: Full NUMERIC "0"\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"\r
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"\r
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"\r
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"\r
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"\r
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"\r
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"\r
+// Retrieval info: PRIVATE: UsedW NUMERIC "0"\r
+// Retrieval info: PRIVATE: Width NUMERIC "32"\r
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"\r
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"\r
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"\r
+// Retrieval info: PRIVATE: output_width NUMERIC "32"\r
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"\r
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"\r
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"\r
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"\r
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"\r
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"\r
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"\r
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"\r
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"\r
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"\r
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"\r
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"\r
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"\r
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"\r
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"\r
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock\r
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]\r
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty\r
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]\r
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq\r
+// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr\r
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq\r
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0\r
+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0\r
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0\r
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0\r
+// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.inc FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.cmp FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.bsf FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_inst.v FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_bb.v FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_waveforms.html FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_wave*.jpg FALSE\r
+// Retrieval info: LIB_FILE: altera_mf\r
projects / debian / gnuradio / blobdiff