--- /dev/null
+// -*- verilog -*-\r
+//\r
+// USRP - Universal Software Radio Peripheral\r
+//\r
+// Copyright (C) 2007 Corgan Enterprises LLC\r
+//\r
+// This program is free software; you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation; either version 2 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// This program is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with this program; if not, write to the Free Software\r
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA\r
+//\r
+\r
+`include "../top/config.vh"\r
+\r
+module dac_interface(clk_i,rst_i,ena_i,strobe_i,tx_i_i,tx_q_i,tx_data_o,tx_sync_o);\r
+ input clk_i;\r
+ input rst_i;\r
+ input ena_i;\r
+ input strobe_i;\r
+ \r
+ input [13:0] tx_i_i;\r
+ input [13:0] tx_q_i;\r
+\r
+ output [13:0] tx_data_o;\r
+ output tx_sync_o;\r
+\r
+`ifdef TX_RATE_MAX\r
+ wire clk128;\r
+ reg clk64_d;\r
+ reg [13:0] tx_data_o;\r
+ \r
+ // Create a 128 MHz clock\r
+ dacpll pll128(.areset(rst_i),.inclk0(clk_i),.c0(clk128));\r
+\r
+ // Register the clk64 clock in the clk128 domain\r
+ always @(posedge clk128)\r
+ clk64_d <= clk_i;\r
+\r
+ // Register the tx data in the clk128 domain\r
+ always @(posedge clk128)\r
+ tx_data_o <= clk64_d ? tx_i_i : tx_q_i;\r
+\r
+ assign tx_sync_o = clk64_d;\r
+ \r
+\r
+`else // !`ifdef TX_RATE_MAX\r
+ assign tx_data_o = strobe_i ? tx_i_i : tx_q_i;\r
+ assign tx_sync_o = strobe_i;\r
+`endif // !`ifdef TX_RATE_MAX\r
+ \r
+endmodule // dac_interface\r