Adds alternative integrate and dump decimator to gr-gpio.

[debian/gnuradio] / gr-gpio / src / fpga / top / usrp_gpio.qsf

diff --git a/gr-gpio/src/fpga/top/usrp_gpio.qsf b/gr-gpio/src/fpga/top/usrp_gpio.qsf
index 4132dccad7cc6bbf18eacedbe18e33180c232394..cfdcd552b62c5cc4d26332d99e1ba3a36f147585 100644 (file)
--- a/gr-gpio/src/fpga/top/usrp_gpio.qsf
+++ b/gr-gpio/src/fpga/top/usrp_gpio.qsf
@@ -375,6 +375,9 @@ set_global_assignment -name VERILOG_FILE ../lib/gpio_input.v
 set_global_assignment -name VERILOG_FILE ../lib/io_pins.v\r
 set_global_assignment -name VERILOG_FILE ../lib/rx_chain_dig.v\r
 set_global_assignment -name VERILOG_FILE ../lib/tx_chain_dig.v\r
+set_global_assignment -name VERILOG_FILE ../lib/integrator.v\r
+set_global_assignment -name VERILOG_FILE ../lib/integ_shifter.v\r
+set_global_assignment -name VERILOG_FILE ../lib/rx_chain.v\r
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v\r
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_dec_shifter.v\r
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v\r
@@ -394,7 +397,6 @@ set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_inter
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v\r
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v\r
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_int_shifter.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_chain.v\r
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v\r
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v\r
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v\r