parse_options(argc, argv, &state);
switch (state.stlink_version) {
case 2:
- sl = stlink_open_usb(state.logging_level, 0);
+ sl = stlink_open_usb(state.logging_level, 0, NULL);
if(sl == NULL) return 1;
break;
case 1:
" <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x10\"/>" // option byte area
"</memory-map>";
+static const char* const memory_map_template_F7 =
+ "<?xml version=\"1.0\"?>"
+ "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
+ " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
+ "<memory-map>"
+ " <memory type=\"ram\" start=\"0x00000000\" length=\"0x4000\"/>" // ITCM ram 16kB
+ " <memory type=\"rom\" start=\"0x00200000\" length=\"0x100000\"/>" // ITCM flash
+ " <memory type=\"ram\" start=\"0x20000000\" length=\"0x50000\"/>" // sram
+ " <memory type=\"flash\" start=\"0x08000000\" length=\"0x20000\">" // Sectors 0..3
+ " <property name=\"blocksize\">0x8000</property>" // 32kB
+ " </memory>"
+ " <memory type=\"flash\" start=\"0x08020000\" length=\"0x20000\">" // Sector 4
+ " <property name=\"blocksize\">0x20000</property>" // 128kB
+ " </memory>"
+ " <memory type=\"flash\" start=\"0x08040000\" length=\"0xC0000\">" // Sectors 5..7
+ " <property name=\"blocksize\">0x40000</property>" // 128kB
+ " </memory>"
+ " <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
+ " <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
+ " <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
+ " <memory type=\"rom\" start=\"0x00100000\" length=\"0xEDC0\"/>" // bootrom
+ " <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x20\"/>" // option byte area
+ "</memory-map>";
+
char* make_memory_map(stlink_t *sl) {
/* This will be freed in serve() */
char* map = malloc(4096);
if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F446) {
strcpy(map, memory_map_template_F4);
+ } else if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F7) {
+ strcpy(map, memory_map_template_F7);
} else if(sl->chip_id==STM32_CHIPID_F4_HD) {
strcpy(map, memory_map_template_F4_HD);
} else if(sl->chip_id==STM32_CHIPID_F2) {
return -1;
}
-#define CODE_BREAK_NUM 6
-#define CODE_LIT_NUM 2
+int code_break_num;
+int code_lit_num;
+#define CODE_BREAK_NUM_MAX 15
#define CODE_BREAK_LOW 0x01
#define CODE_BREAK_HIGH 0x02
int type;
};
-struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM];
+struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX];
static void init_code_breakpoints(stlink_t *sl) {
memset(sl->q_buf, 0, 4);
stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/);
unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL);
- if (((val & 3) != 1) ||
- ((((val >> 8) & 0x70) | ((val >> 4) & 0xf)) != CODE_BREAK_NUM) ||
- (((val >> 8) & 0xf) != CODE_LIT_NUM)){
- ELOG("[FP_CTRL] = 0x%08x expecting 0x%08x\n", val,
- ((CODE_BREAK_NUM & 0x70) << 8) | (CODE_LIT_NUM << 8) | ((CODE_BREAK_NUM & 0xf) << 4) | 1);
- }
+ code_break_num = ((val >> 4) & 0xf);
+ code_lit_num = ((val >> 8) & 0xf);
+ ILOG("Found %i hw breakpoint registers\n", code_break_num);
- for(int i = 0; i < CODE_BREAK_NUM; i++) {
+ for(int i = 0; i < code_break_num; i++) {
code_breaks[i].type = 0;
stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0);
}
}
static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) {
- stm32_addr_t fpb_addr = addr & ~0x3;
- int type = addr & 0x2 ? CODE_BREAK_HIGH : CODE_BREAK_LOW;
+ stm32_addr_t fpb_addr;
+ uint32_t mask;
+ int type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW;
if(addr & 1) {
ELOG("update_code_breakpoint: unaligned address %08x\n", addr);
return -1;
}
+ if (sl->chip_id==STM32_CHIPID_F7) {
+ fpb_addr = addr;
+ } else {
+ fpb_addr = addr & ~0x3;
+ }
+
int id = -1;
- for(int i = 0; i < CODE_BREAK_NUM; i++) {
+ for(int i = 0; i < code_break_num; i++) {
if(fpb_addr == code_breaks[i].addr ||
(set && code_breaks[i].type == 0)) {
id = i;
brk->addr = fpb_addr;
- if(set) brk->type |= type;
- else brk->type &= ~type;
+ if (sl->chip_id==STM32_CHIPID_F7) {
+ if(set) brk->type = type;
+ else brk->type = 0;
+
+ mask = (brk->addr) | 1;
+ } else {
+ if(set) brk->type |= type;
+ else brk->type &= ~type;
+
+ mask = (brk->addr) | 1 | (brk->type << 30);
+ }
if(brk->type == 0) {
DLOG("clearing hw break %d\n", id);
stlink_write_debug32(sl, 0xe0002008 + id * 4, 0);
} else {
- uint32_t mask = (brk->addr) | 1 | (brk->type << 30);
-
DLOG("setting hw break %d at %08x (%d)\n",
id, brk->addr, brk->type);
DLOG("reg %08x \n",
// Some kinds of clock settings do not allow writing to flash.
stlink_reset(sl);
+ stlink_force_debug(sl);
for(struct flash_block* fb = flash_root; fb; fb = fb->next) {
DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length);
- unsigned length = fb->length;
for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) {
+ unsigned length = fb->length - (page - fb->addr);
//Update FLASH_PAGE
stlink_calculate_pagesize(sl, page);
DLOG("flash_do: page %08x\n", page);
-
+ unsigned send = length > FLASH_PAGE ? FLASH_PAGE : length;
if(stlink_write_flash(sl, page, fb->data + (page - fb->addr),
- length > FLASH_PAGE ? FLASH_PAGE : length) < 0)
+ send) < 0)
goto error;
+ length -= send;
+
}
}
DLOG("query: %s;%s\n", queryName, params);
if(!strcmp(queryName, "Supported")) {
- if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F4_HD) {
+ if(sl->chip_id==STM32_CHIPID_F4
+ || sl->chip_id==STM32_CHIPID_F4_HD
+ || sl->chip_id==STM32_CHIPID_F7) {
reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+");
}
else {
projects / fw / stlink / blobdiff