" <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
"</memory-map>";
+static const char* const memory_map_template_L4 =
+ "<?xml version=\"1.0\"?>"
+ "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
+ " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
+ "<memory-map>"
+ " <memory type=\"rom\" start=\"0x00000000\" length=\"0x%zx\"/>" // code = sram, bootrom or flash; flash is bigger
+ " <memory type=\"ram\" start=\"0x10000000\" length=\"0x8000\"/>" // SRAM2 (32 KB)
+ " <memory type=\"ram\" start=\"0x20000000\" length=\"0x18000\"/>" // SRAM1 (96 KB)
+ " <memory type=\"flash\" start=\"0x08000000\" length=\"0x%zx\">"
+ " <property name=\"blocksize\">0x800</property>"
+ " </memory>"
+ " <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
+ " <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
+ " <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
+ " <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7000\"/>" // bootrom
+ " <memory type=\"rom\" start=\"0x1fff7800\" length=\"0x10\"/>" // option byte area
+ " <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x10\"/>" // option byte area
+ "</memory-map>";
+
static const char* const memory_map_template =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
sl->sram_size,
sl->flash_size - 0x20000,
sl->sys_base, sl->sys_size);
+ } else if(sl->chip_id==STM32_CHIPID_L4) {
+ snprintf(map, 4096, memory_map_template_L4,
+ sl->flash_size, sl->flash_size);
} else {
snprintf(map, 4096, memory_map_template,
sl->flash_size,
static unsigned ceil_log2(unsigned v)
{
unsigned res;
- for (res = 0; (1 << res) < v; res++)
+ for (res = 0; (1U << res) < v; res++)
;
return res;
}