#include <sys/socket.h>
#include <netinet/in.h>
#include <arpa/inet.h>
+
+#include <stlink-common.h>
+
#include "gdb-remote.h"
-#include "stlink-hw.h"
#define FLASH_BASE 0x08000000
#define FLASH_PAGE (sl->flash_pgsz)
static const char* current_memory_map = NULL;
+/*
+ * Chip IDs are explained in the appropriate programming manual for the
+ * DBGMCU_IDCODE register (0xE0042000)
+ */
struct chip_params {
uint32_t chip_id;
char* description;
uint32_t sram_size;
uint32_t bootrom_base, bootrom_size;
} const devices[] = {
- { 0x412, "Low-density device",
- 0x8000, 0x400, 0x2800, 0x1ffff000, 0x800 },
- { 0x410, "Medium-density device",
- 0x20000, 0x400, 0x5000, 0x1ffff000, 0x800 },
- { 0x414, "High-density device",
- 0x80000, 0x800, 0x10000, 0x1ffff000, 0x800 },
- { 0x418, "Connectivity line device",
+ { 0x410, "F1 Medium-density device",
+ 0x20000, 0x400, 0x5000, 0x1ffff000, 0x800 }, // table 2, pm0063
+ { 0x411, "F2 device",
+ 0x100000, 0x20000, 0x20000, 0x1ff00000, 0x7800 }, // table 1, pm0059
+ { 0x412, "F1 Low-density device",
+ 0x8000, 0x400, 0x2800, 0x1ffff000, 0x800 }, // table 1, pm0063
+ { 0x413, "F4 device",
+ 0x100000, 0x20000, 0x20000, 0x1ff00000, 0x7800 }, // table 1, pm0081
+ { 0x414, "F1 High-density device",
+ 0x80000, 0x800, 0x10000, 0x1ffff000, 0x800 }, // table 3 pm0063
+ // This ignores the EEPROM! (and uses the page erase size,
+ // not the sector write protection...)
+ { 0x416, "L1 Med-density device", // table 1, pm0062
+ 0x20000, 0x100, 0x4000, 0x1ff00000, 0x1000 },
+ { 0x418, "F1 Connectivity line device",
0x40000, 0x800, 0x10000, 0x1fffb000, 0x4800 },
- { 0x420, "Medium-density value line device",
+ { 0x420, "F1 Medium-density value line device",
0x20000, 0x400, 0x2000, 0x1ffff000, 0x800 },
- { 0x428, "High-density value line device",
+ { 0x428, "F1 High-density value line device",
0x80000, 0x800, 0x8000, 0x1ffff000, 0x800 },
- { 0x430, "XL-density device",
+ { 0x430, "F1 XL-density device", // pm0068
0x100000, 0x800, 0x18000, 0x1fffe000, 0x1800 },
{ 0 }
};
-int serve(struct stlink* sl, int port);
+int serve(stlink_t *sl, int port);
char* make_memory_map(const struct chip_params *params, uint32_t flash_size);
int main(int argc, char** argv) {
return 1;
}
- struct stlink *sl = stlink_quirk_open(argv[2], 0);
+ // FIXME - hardcoded to usb....
+ stlink_t *sl =stlink_open_usb(argv[2], 10);
if (sl == NULL)
return 1;
if(stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE)
stlink_enter_swd_mode(sl);
- uint32_t chip_id;
-
- stlink_read_mem32(sl, 0xE0042000, 4);
- chip_id = sl->q_buf[0] | (sl->q_buf[1] << 8) | (sl->q_buf[2] << 16) |
- (sl->q_buf[3] << 24);
-
+ uint32_t chip_id = stlink_chip_id(sl);
printf("Chip ID is %08x.\n", chip_id);
const struct chip_params* params = NULL;
uint32_t flash_size;
- stlink_read_mem32(sl, 0x1FFFF7E0, 4);
+ stlink_read_mem32(sl, 0x1FFFF7E0, 4); // FIXME - that's never going to work!
flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8);
printf("Flash size is %d KiB.\n", flash_size);
struct code_hw_watchpoint data_watches[DATA_WATCH_NUM];
-static void init_data_watchpoints(struct stlink *sl) {
- int i;
-
+static void init_data_watchpoints(stlink_t *sl) {
#ifdef DEBUG
printf("init watchpoints\n");
#endif
}
}
-static int add_data_watchpoint(struct stlink* sl, enum watchfun wf, stm32_addr_t addr, unsigned int len)
+static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len)
{
int i = 0;
- uint32_t mask, temp;
+ uint32_t mask;
// computer mask
// find a free watchpoint
return -1;
}
-static int delete_data_watchpoint(struct stlink* sl, stm32_addr_t addr)
+static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr)
{
int i;
struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM];
-static void init_code_breakpoints(struct stlink* sl) {
+static void init_code_breakpoints(stlink_t *sl) {
memset(sl->q_buf, 0, 4);
sl->q_buf[0] = 0x03; // KEY | ENABLE
stlink_write_mem32(sl, 0xe0002000, 4);
}
}
-static int update_code_breakpoint(struct stlink* sl, stm32_addr_t addr, int set) {
+static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) {
stm32_addr_t fpb_addr = addr & ~0x3;
int type = addr & 0x2 ? CODE_BREAK_HIGH : CODE_BREAK_LOW;
static struct flash_block* flash_root;
static int flash_add_block(stm32_addr_t addr, unsigned length,
- struct stlink* sl) {
+ stlink_t *sl) {
if(addr < FLASH_BASE || addr + length > FLASH_BASE + FLASH_SIZE) {
fprintf(stderr, "flash_add_block: incorrect bounds\n");
return -1;
return 0;
}
-static int flash_go(struct stlink* sl) {
+static int flash_go(stlink_t *sl) {
int error = -1;
// Some kinds of clock settings do not allow writing to flash.
return error;
}
-int serve(struct stlink* sl, int port) {
+int serve(stlink_t *sl, int port) {
int sock = socket(AF_INET, SOCK_STREAM, 0);
if(sock < 0) {
perror("socket");
#endif
char* reply = NULL;
+ reg regp;
switch(packet[0]) {
case 'q': {
break;
case 'g':
- stlink_read_all_regs(sl);
+ stlink_read_all_regs(sl, ®p);
reply = calloc(8 * 16 + 1, 1);
for(int i = 0; i < 16; i++)
- sprintf(&reply[i * 8], "%08x", htonl(sl->reg.r[i]));
+ sprintf(&reply[i * 8], "%08x", htonl(regp.r[i]));
break;
case 'p': {
- unsigned id = strtoul(&packet[1], NULL, 16), reg = 0xDEADDEAD;
+ unsigned id = strtoul(&packet[1], NULL, 16);
+ unsigned myreg = 0xDEADDEAD;
if(id < 16) {
- stlink_read_reg(sl, id);
- reg = htonl(sl->reg.r[id]);
+ stlink_read_reg(sl, id, ®p);
+ myreg = htonl(regp.r[id]);
} else if(id == 0x19) {
- stlink_read_reg(sl, 16);
- reg = htonl(sl->reg.xpsr);
+ stlink_read_reg(sl, 16, ®p);
+ myreg = htonl(regp.xpsr);
} else {
reply = strdup("E00");
}
reply = calloc(8 + 1, 1);
- sprintf(reply, "%08x", reg);
+ sprintf(reply, "%08x", myreg);
break;
}
case 'z': {
char *endptr;
stm32_addr_t addr = strtoul(&packet[3], &endptr, 16);
- stm32_addr_t len = strtoul(&endptr[1], NULL, 16);
+ //stm32_addr_t len = strtoul(&endptr[1], NULL, 16);
switch (packet[1]) {
case '1': // remove breakpoint
projects / fw / stlink / blobdiff