+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_tim.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the TIM peripheral:\r
- * - TimeBase management\r
- * - Output Compare management\r
- * - Input Capture management\r
- * - Interrupts, DMA and flags management\r
- * - Clocks management\r
- * - Synchronization management\r
- * - Specific interface management\r
- * - Specific remapping management \r
- * \r
- * @verbatim\r
- * \r
- * ===================================================================\r
- * How to use this driver\r
- * ===================================================================\r
- * This driver provides functions to configure and program the TIM \r
- * of all STM32L1xx devices\r
- * These functions are split in 8 groups: \r
- * \r
- * 1. TIM TimeBase management: this group includes all needed functions \r
- * to configure the TM Timebase unit:\r
- * - Set/Get Prescaler\r
- * - Set/Get Autoreload \r
- * - Counter modes configuration\r
- * - Set Clock division \r
- * - Select the One Pulse mode\r
- * - Update Request Configuration\r
- * - Update Disable Configuration\r
- * - Auto-Preload Configuration \r
- * - Enable/Disable the counter \r
- * \r
- * 2. TIM Output Compare management: this group includes all needed \r
- * functions to configure the Capture/Compare unit used in Output \r
- * compare mode: \r
- * - Configure each channel, independently, in Output Compare mode\r
- * - Select the output compare modes\r
- * - Select the Polarities of each channel\r
- * - Set/Get the Capture/Compare register values\r
- * - Select the Output Compare Fast mode \r
- * - Select the Output Compare Forced mode \r
- * - Output Compare-Preload Configuration \r
- * - Clear Output Compare Reference\r
- * - Select the OCREF Clear signal\r
- * - Enable/Disable the Capture/Compare Channels \r
- * \r
- * 3. TIM Input Capture management: this group includes all needed \r
- * functions to configure the Capture/Compare unit used in \r
- * Input Capture mode:\r
- * - Configure each channel in input capture mode\r
- * - Configure Channel1/2 in PWM Input mode\r
- * - Set the Input Capture Prescaler\r
- * - Get the Capture/Compare values \r
- * \r
- * 4. TIM interrupts, DMA and flags management\r
- * - Enable/Disable interrupt sources\r
- * - Get flags status\r
- * - Clear flags/ Pending bits\r
- * - Enable/Disable DMA requests \r
- * - Configure DMA burst mode\r
- * - Select CaptureCompare DMA request \r
- * \r
- * 5. TIM clocks management: this group includes all needed functions \r
- * to configure the clock controller unit:\r
- * - Select internal/External clock\r
- * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx\r
- * \r
- * 6. TIM synchronization management: this group includes all needed \r
- * functions to configure the Synchronization unit:\r
- * - Select Input Trigger \r
- * - Select Output Trigger \r
- * - Select Master Slave Mode \r
- * - ETR Configuration when used as external trigger \r
- * \r
- * 7. TIM specific interface management, this group includes all \r
- * needed functions to use the specific TIM interface:\r
- * - Encoder Interface Configuration\r
- * - Select Hall Sensor \r
- * \r
- * 8. TIM specific remapping management includes the Remapping \r
- * configuration of specific timers \r
- * \r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_tim.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup TIM \r
- * @brief TIM driver modules\r
- * @{\r
- */\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/* ---------------------- TIM registers bit mask ------------------------ */\r
-#define SMCR_ETR_MASK ((uint16_t)0x00FF) \r
-#define CCMR_OFFSET ((uint16_t)0x0018)\r
-#define CCER_CCE_SET ((uint16_t)0x0001) \r
- \r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-\r
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup TIM_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup TIM_Group1 TimeBase management functions\r
- * @brief TimeBase management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- TimeBase management functions\r
- =============================================================================== \r
- \r
- =================================================================== \r
- TIM Driver: how to use it in Timing(Time base) Mode\r
- =================================================================== \r
- To use the Timer in Timing(Time base) mode, the following steps are mandatory:\r
- \r
- 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r
- \r
- 2. Fill the TIM_TimeBaseInitStruct with the desired parameters.\r
- \r
- 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit\r
- with the corresponding configuration\r
- \r
- 4. Enable the NVIC if you need to generate the update interrupt. \r
- \r
- 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) \r
- \r
- 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
- \r
- Note1: All other functions can be used seperatly to modify, if needed,\r
- a specific feature of the Timer. \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @retval None\r
- * \r
- */\r
-void TIM_DeInit(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
- \r
- if (TIMx == TIM2)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);\r
- }\r
- else if (TIMx == TIM3)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);\r
- }\r
- else if (TIMx == TIM4)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);\r
- } \r
-\r
- else if (TIMx == TIM6)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);\r
- } \r
- else if (TIMx == TIM7)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);\r
- } \r
-\r
- else if (TIMx == TIM9)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);\r
- } \r
- else if (TIMx == TIM10)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);\r
- } \r
- else\r
- {\r
- if (TIMx == TIM11)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); \r
- } \r
- }\r
- \r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Time Base Unit peripheral according to \r
- * the specified parameters in the TIM_TimeBaseInitStruct.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef\r
- * structure that contains the configuration information for\r
- * the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
-{\r
- uint16_t tmpcr1 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));\r
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));\r
-\r
- tmpcr1 = TIMx->CR1; \r
-\r
- if(((TIMx) == TIM2) || ((TIMx) == TIM3) || ((TIMx) == TIM4))\r
- { \r
- /* Select the Counter Mode */\r
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;\r
- }\r
- \r
- if(((TIMx) != TIM6) && ((TIMx) != TIM7))\r
- {\r
- /* Set the clock division */\r
- tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));\r
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;\r
- }\r
-\r
- TIMx->CR1 = tmpcr1;\r
-\r
- /* Set the Autoreload value */\r
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;\r
- \r
- /* Set the Prescaler value */\r
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;\r
- \r
- /* Generate an update event to reload the Prescaler value immediatly */\r
- TIMx->EGR = TIM_PSCReloadMode_Immediate; \r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.\r
- * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef\r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;\r
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;\r
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;\r
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Prescaler.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param Prescaler: specifies the Prescaler Register value\r
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode\r
- * This parameter can be one of the following values:\r
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.\r
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.\r
- * @retval None\r
- */\r
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));\r
- \r
- /* Set the Prescaler value */\r
- TIMx->PSC = Prescaler;\r
- /* Set or reset the UG Bit */\r
- TIMx->EGR = TIM_PSCReloadMode;\r
-}\r
-\r
-/**\r
- * @brief Specifies the TIMx Counter Mode to be used.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_CounterMode: specifies the Counter Mode to be used\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode\r
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode\r
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1\r
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2\r
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3\r
- * @retval None\r
- */\r
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)\r
-{\r
- uint16_t tmpcr1 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));\r
- \r
- tmpcr1 = TIMx->CR1;\r
- /* Reset the CMS and DIR Bits */\r
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
- /* Set the Counter Mode */\r
- tmpcr1 |= TIM_CounterMode;\r
- /* Write to TIMx CR1 register */\r
- TIMx->CR1 = tmpcr1;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Counter Register value\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param Counter: specifies the Counter register new value.\r
- * @retval None\r
- */\r
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- \r
- /* Set the Counter Register value */\r
- TIMx->CNT = Counter;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Autoreload Register value\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param Autoreload: specifies the Autoreload register new value.\r
- * @retval None\r
- */\r
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- \r
- /* Set the Autoreload Register value */\r
- TIMx->ARR = Autoreload;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Counter value.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @retval Counter Register value.\r
- */\r
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- \r
- /* Get the Counter Register value */\r
- return TIMx->CNT;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Prescaler value.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @retval Prescaler Register value.\r
- */\r
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- \r
- /* Get the Prescaler Register value */\r
- return TIMx->PSC;\r
-}\r
-\r
-/**\r
- * @brief Enables or Disables the TIMx Update event.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param NewState: new state of the TIMx UDIS bit\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Set the Update Disable Bit */\r
- TIMx->CR1 |= TIM_CR1_UDIS;\r
- }\r
- else\r
- {\r
- /* Reset the Update Disable Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Update Request Interrupt source.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_UpdateSource: specifies the Update source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow\r
- or the setting of UG bit, or an update generation\r
- through the slave mode controller.\r
- * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.\r
- * @retval None\r
- */\r
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));\r
- \r
- if (TIM_UpdateSource != TIM_UpdateSource_Global)\r
- {\r
- /* Set the URS Bit */\r
- TIMx->CR1 |= TIM_CR1_URS;\r
- }\r
- else\r
- {\r
- /* Reset the URS Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables TIMx peripheral Preload register on ARR.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param NewState: new state of the TIMx peripheral Preload register\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Set the ARR Preload Bit */\r
- TIMx->CR1 |= TIM_CR1_ARPE;\r
- }\r
- else\r
- {\r
- /* Reset the ARR Preload Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx\92s One Pulse Mode.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_OPMode: specifies the OPM Mode to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OPMode_Single\r
- * @arg TIM_OPMode_Repetitive\r
- * @retval None\r
- */\r
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));\r
- \r
- /* Reset the OPM Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);\r
- /* Configure the OPM Mode */\r
- TIMx->CR1 |= TIM_OPMode;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Clock Division value.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_CKD: specifies the clock division value.\r
- * This parameter can be one of the following value:\r
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim\r
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim\r
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim\r
- * @retval None\r
- */\r
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));\r
- \r
- /* Reset the CKD Bits */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);\r
- /* Set the CKD value */\r
- TIMx->CR1 |= TIM_CKD;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified TIM peripheral.\r
- * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.\r
- * @param NewState: new state of the TIMx peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the TIM Counter */\r
- TIMx->CR1 |= TIM_CR1_CEN;\r
- }\r
- else\r
- {\r
- /* Disable the TIM Counter */\r
- TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group2 Output Compare management functions\r
- * @brief Output Compare management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Output Compare management functions\r
- =============================================================================== \r
- \r
- =================================================================== \r
- TIM Driver: how to use it in Output Compare Mode\r
- =================================================================== \r
- To use the Timer in Output Compare mode, the following steps are mandatory:\r
- \r
- 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r
- \r
- 2. Configure the TIM pins by configuring the corresponding GPIO pins\r
- \r
- 2. Configure the Time base unit as described in the first part of this driver, if needed,\r
- else the Timer will run with the default configuration:\r
- - Autoreload value = 0xFFFF\r
- - Prescaler value = 0x0000\r
- - Counter mode = Up counting\r
- - Clock Division = TIM_CKD_DIV1\r
- \r
- 3. Fill the TIM_OCInitStruct with the desired parameters including:\r
- - The TIM Output Compare mode: TIM_OCMode\r
- - TIM Output State: TIM_OutputState\r
- - TIM Pulse value: TIM_Pulse\r
- - TIM Output Compare Polarity : TIM_OCPolarity\r
- \r
- 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the \r
- corresponding configuration\r
- \r
- 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
- \r
- Note1: All other functions can be used separately to modify, if needed,\r
- a specific feature of the Timer. \r
- \r
- Note2: In case of PWM mode, this function is mandatory:\r
- TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); \r
- \r
- Note3: If the corresponding interrupt or DMA request are needed, the user should:\r
- 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). \r
- 2. Enable the corresponding interrupt (or DMA request) using the function \r
- TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel1 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM \r
- * peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
- /* Disable the Channel 1: Reset the CC1E Bit */\r
- TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);\r
- \r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmrx = TIMx->CCMR1;\r
- \r
- /* Reset the Output Compare Mode Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));\r
- \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;\r
- \r
- /* Set the Output State */\r
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;\r
- \r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmrx;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel2 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM \r
- * peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx)); \r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));\r
- \r
- /* Get the TIMx CCER register value */ \r
- tmpccer = TIMx->CCER;\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmrx = TIMx->CCMR1;\r
- \r
- /* Reset the Output Compare Mode Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));\r
- \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);\r
- \r
- /* Set the Output State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);\r
- \r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmrx;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel3 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM \r
- * peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
-\r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));\r
- \r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- \r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmrx = TIMx->CCMR2;\r
- \r
- /* Reset the Output Compare Mode Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));\r
- \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);\r
- \r
- /* Set the Output State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);\r
- \r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmrx;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel4 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM \r
- * peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
-\r
- /* Disable the Channel 2: Reset the CC4E Bit */\r
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));\r
- \r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- \r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmrx = TIMx->CCMR2;\r
- \r
- /* Reset the Output Compare Mode Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));\r
- \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);\r
- \r
- /* Set the Output State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);\r
- \r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCMR2 */ \r
- TIMx->CCMR2 = tmpccmrx;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_OCInitStruct member with its default value.\r
- * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;\r
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;\r
- TIM_OCInitStruct->TIM_Pulse = 0x0000;\r
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;\r
-}\r
-\r
-/**\r
- * @brief Selects the TIM Output Compare Mode.\r
- * @note This function disables the selected channel before changing the Output\r
- * Compare Mode.\r
- * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_Channel: specifies the TIM Channel\r
- * This parameter can be one of the following values:\r
- * @arg TIM_Channel_1: TIM Channel 1\r
- * @arg TIM_Channel_2: TIM Channel 2\r
- * @arg TIM_Channel_3: TIM Channel 3\r
- * @arg TIM_Channel_4: TIM Channel 4\r
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCMode_Timing\r
- * @arg TIM_OCMode_Active\r
- * @arg TIM_OCMode_Toggle\r
- * @arg TIM_OCMode_PWM1\r
- * @arg TIM_OCMode_PWM2\r
- * @arg TIM_ForcedAction_Active\r
- * @arg TIM_ForcedAction_InActive\r
- * @retval None\r
- */\r
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)\r
-{\r
- uint32_t tmp = 0;\r
- uint16_t tmp1 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
- assert_param(IS_TIM_OCM(TIM_OCMode));\r
- \r
- tmp = (uint32_t) TIMx;\r
- tmp += CCMR_OFFSET;\r
-\r
- tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;\r
-\r
- /* Disable the Channel: Reset the CCxE Bit */\r
- TIMx->CCER &= (uint16_t) ~tmp1;\r
-\r
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))\r
- {\r
- tmp += (TIM_Channel>>1);\r
-\r
- /* Reset the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);\r
- \r
- /* Configure the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp |= TIM_OCMode;\r
- }\r
- else\r
- {\r
- tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;\r
-\r
- /* Reset the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);\r
- \r
- /* Configure the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare1 Register value\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param Compare1: specifies the Capture Compare1 register new value.\r
- * @retval None\r
-\r
- */\r
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- \r
- /* Set the Capture Compare1 Register value */\r
- TIMx->CCR1 = Compare1;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare2 Register value\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param Compare2: specifies the Capture Compare2 register new value.\r
- * @retval None\r
-\r
- */\r
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- \r
- /* Set the Capture Compare2 Register value */\r
- TIMx->CCR2 = Compare2;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare3 Register value\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param Compare3: specifies the Capture Compare3 register new value.\r
- * @retval None\r
-\r
- */\r
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- \r
- /* Set the Capture Compare3 Register value */\r
- TIMx->CCR3 = Compare3;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare4 Register value\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param Compare4: specifies the Capture Compare4 register new value.\r
- * @retval None\r
-\r
- */\r
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- \r
- /* Set the Capture Compare4 Register value */\r
- TIMx->CCR4 = Compare4;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 1 waveform to active or inactive level.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1M Bits */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr1 |= TIM_ForcedAction;\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
- \r
-/**\r
- * @brief Forces the TIMx output 2 waveform to active or inactive level.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM \r
- * peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- \r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2M Bits */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 3 waveform to active or inactive level.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- \r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC1M Bits */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr2 |= TIM_ForcedAction;\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 4 waveform to active or inactive level.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- \r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC2M Bits */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- \r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1PE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr1 |= TIM_OCPreload;\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- \r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2PE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- \r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC3PE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr2 |= TIM_OCPreload;\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- \r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC4PE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 1 Fast feature.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1FE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr1 |= TIM_OCFast;\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 2 Fast feature.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2FE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 3 Fast feature.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- \r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC3FE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr2 |= TIM_OCFast;\r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 4 Fast feature.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- \r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC4FE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);\r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF1 signal on an external event\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- \r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1CE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr1 |= TIM_OCClear;\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF2 signal on an external event\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
-\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- \r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2CE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF3 signal on an external event\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- \r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC3CE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr2 |= TIM_OCClear;\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF4 signal on an external event\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- \r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC4CE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 1 polarity.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC1 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC1P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);\r
- tmpccer |= TIM_OCPolarity;\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 2 polarity.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC2 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC2P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);\r
- tmpccer |= (uint16_t)(TIM_OCPolarity << 4);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 3 polarity.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC3 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC3P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);\r
- tmpccer |= (uint16_t)(TIM_OCPolarity << 8);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 4 polarity.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC4 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC4P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);\r
- tmpccer |= (uint16_t)(TIM_OCPolarity << 12);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Selects the OCReference Clear source.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_OCReferenceClear: specifies the OCReference Clear source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.\r
- * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. \r
- * @retval None\r
- */\r
-void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));\r
-\r
- /* Set the TIM_OCReferenceClear source */\r
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);\r
- TIMx->SMCR |= TIM_OCReferenceClear;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIM Capture Compare Channel x.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_Channel: specifies the TIM Channel\r
- * This parameter can be one of the following values:\r
- * @arg TIM_Channel_1: TIM Channel 1\r
- * @arg TIM_Channel_2: TIM Channel 2\r
- * @arg TIM_Channel_3: TIM Channel 3\r
- * @arg TIM_Channel_4: TIM Channel 4\r
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.\r
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. \r
- * @retval None\r
- */\r
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)\r
-{\r
- uint16_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
- assert_param(IS_TIM_CCX(TIM_CCx));\r
-\r
- tmp = CCER_CCE_SET << TIM_Channel;\r
-\r
- /* Reset the CCxE Bit */\r
- TIMx->CCER &= (uint16_t)~ tmp;\r
-\r
- /* Set or reset the CCxE Bit */ \r
- TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group3 Input Capture management functions\r
- * @brief Input Capture management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Input Capture management functions\r
- =============================================================================== \r
- \r
- =================================================================== \r
- TIM Driver: how to use it in Input Capture Mode\r
- =================================================================== \r
- To use the Timer in Input Capture mode, the following steps are mandatory:\r
- \r
- 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function\r
- \r
- 2. Configure the TIM pins by configuring the corresponding GPIO pins\r
- \r
- 2. Configure the Time base unit as described in the first part of this driver, if needed,\r
- else the Timer will run with the default configuration:\r
- - Autoreload value = 0xFFFF\r
- - Prescaler value = 0x0000\r
- - Counter mode = Up counting\r
- - Clock Division = TIM_CKD_DIV1\r
- \r
- 3. Fill the TIM_ICInitStruct with the desired parameters including:\r
- - TIM Channel: TIM_Channel\r
- - TIM Input Capture polarity: TIM_ICPolarity\r
- - TIM Input Capture selection: TIM_ICSelection\r
- - TIM Input Capture Prescaler: TIM_ICPrescaler\r
- - TIM Input CApture filter value: TIM_ICFilter\r
- \r
- 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the \r
- corresponding configuration and to measure only frequency or duty cycle of the input signal,\r
- or,\r
- Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the \r
- corresponding configuration and to measure the frequency and the duty cycle of the input signal\r
- \r
- 5. Enable the NVIC or the DMA to read the measured frequency. \r
- \r
- 6. Enable the corresponding interrupt (or DMA request) to read the Captured value,\r
- using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) \r
- \r
- 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
- \r
- 8. Use TIM_GetCapturex(TIMx); to read the captured value.\r
- \r
- Note1: All other functions can be used seperatly to modify, if needed,\r
- a specific feature of the Timer. \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Initializes the TIM peripheral according to the specified\r
- * parameters in the TIM_ICInitStruct.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
- * that contains the configuration information for the specified TIM \r
- * peripheral.\r
- * @retval None\r
- */\r
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));\r
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));\r
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));\r
- \r
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
- {\r
- /* TI1 Configuration */\r
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)\r
- {\r
- /* TI2 Configuration */\r
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)\r
- {\r
- /* TI3 Configuration */\r
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else\r
- {\r
- /* TI4 Configuration */\r
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_ICInitStruct member with its default value.\r
- * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;\r
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;\r
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;\r
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;\r
- TIM_ICInitStruct->TIM_ICFilter = 0x00;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIM peripheral according to the specified\r
- * parameters in the TIM_ICInitStruct to measure an external PWM signal.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
- * that contains the configuration information for the specified TIM \r
- * peripheral.\r
- * @retval None\r
- */\r
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
-{\r
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;\r
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- /* Select the Opposite Input Polarity */\r
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)\r
- {\r
- icoppositepolarity = TIM_ICPolarity_Falling;\r
- }\r
- else\r
- {\r
- icoppositepolarity = TIM_ICPolarity_Rising;\r
- }\r
- /* Select the Opposite Input */\r
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)\r
- {\r
- icoppositeselection = TIM_ICSelection_IndirectTI;\r
- }\r
- else\r
- {\r
- icoppositeselection = TIM_ICSelection_DirectTI;\r
- }\r
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
- {\r
- /* TI1 Configuration */\r
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- /* TI2 Configuration */\r
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else\r
- { \r
- /* TI2 Configuration */\r
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- /* TI1 Configuration */\r
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 1 value.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @retval Capture Compare 1 Register value.\r
-\r
- */\r
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- \r
- /* Get the Capture 1 Register value */\r
- return TIMx->CCR1;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 2 value.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @retval Capture Compare 2 Register value.\r
-\r
- */\r
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- \r
- /* Get the Capture 2 Register value */\r
- return TIMx->CCR2;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 3 value.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @retval Capture Compare 3 Register value.\r
- */\r
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
- \r
- /* Get the Capture 3 Register value */\r
- return TIMx->CCR3;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 4 value.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @retval Capture Compare 4 Register value.\r
- */\r
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- \r
- /* Get the Capture 4 Register value */\r
- return TIMx->CCR4;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 1 prescaler.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- \r
- /* Reset the IC1PSC Bits */\r
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);\r
- /* Set the IC1PSC value */\r
- TIMx->CCMR1 |= TIM_ICPSC;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 2 prescaler.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- \r
- /* Reset the IC2PSC Bits */\r
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);\r
- /* Set the IC2PSC value */\r
- TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 3 prescaler.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- \r
- /* Reset the IC3PSC Bits */\r
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);\r
- /* Set the IC3PSC value */\r
- TIMx->CCMR2 |= TIM_ICPSC;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 4 prescaler.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- \r
- /* Reset the IC4PSC Bits */\r
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);\r
- /* Set the IC4PSC value */\r
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group4 Interrupts DMA and flags management functions\r
- * @brief Interrupts, DMA and flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts, DMA and flags management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified TIM interrupts.\r
- * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.\r
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_IT_Update: TIM update Interrupt source\r
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
- * @note \r
- * - TIM6 and TIM7 can only generate an update interrupt. \r
- * - TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11\r
- * - TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9. \r
- * @param NewState: new state of the TIM interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_IT(TIM_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the Interrupt sources */\r
- TIMx->DIER |= TIM_IT;\r
- }\r
- else\r
- {\r
- /* Disable the Interrupt sources */\r
- TIMx->DIER &= (uint16_t)~TIM_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx event to be generate by software.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_EventSource: specifies the event source.\r
- * This parameter can be one or more of the following values: \r
- * @arg TIM_EventSource_Update: Timer update Event source\r
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source\r
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source\r
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source\r
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source \r
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source\r
- * @note \r
- * - TIM6 and TIM7 can only generate an update event. \r
- * - TIM9 can only generate an update event, Capture Compare 1 event, \r
- * Capture Compare 2 event and TIM_EventSource_Trigger. \r
- * - TIM10 and TIM11 can only generate an update event and Capture Compare 1 event. \r
- * @retval None\r
- */\r
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); \r
- /* Set the event sources */\r
- TIMx->EGR = TIM_EventSource;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified TIM flag is set or not.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_FLAG_Update: TIM update Flag\r
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
- * @note\r
- * - TIM6 and TIM7 can have only one update flag.\r
- * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger,\r
- * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags \r
- * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags \r
- * @retval The new state of TIM_FLAG (SET or RESET).\r
- */\r
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
-{ \r
- ITStatus bitstatus = RESET; \r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));\r
- \r
- if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the TIMx's pending flags.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_FLAG: specifies the flag bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_FLAG_Update: TIM update Flag\r
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
- * @note\r
- * - TIM6 and TIM7 can have only one update flag. \r
- * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags\r
- * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags \r
- * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1\r
- * or TIM_FLAG_CC1OF flags \r
- * @retval None\r
- */\r
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));\r
- \r
- /* Clear the flags */\r
- TIMx->SR = (uint16_t)~TIM_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the TIM interrupt has occurred or not.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_IT: specifies the TIM interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_IT_Update: TIM update Interrupt source\r
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
- * @note\r
- * - TIM6 and TIM7 can generate only an update interrupt.\r
- * - TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2,\r
- * interrupt and TIM_IT_Trigger interrupt.\r
- * - TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1\r
- * interrupt \r
- * @retval The new state of the TIM_IT(SET or RESET).\r
- */\r
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
-{\r
- ITStatus bitstatus = RESET; \r
- uint16_t itstatus = 0x0, itenable = 0x0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_GET_IT(TIM_IT));\r
- \r
- itstatus = TIMx->SR & TIM_IT;\r
- \r
- itenable = TIMx->DIER & TIM_IT;\r
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the TIMx's interrupt pending bits.\r
- * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
- * @param TIM_IT: specifies the pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_IT_Update: TIM update Interrupt source\r
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
- * @note\r
- * - TIM6 and TIM7 can generate only an update interrupt.\r
- * - TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2,\r
- * and TIM_IT_Trigger interrupt. \r
- * - TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1\r
- * interrupt \r
- * @retval None\r
- */\r
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_IT(TIM_IT));\r
- \r
- /* Clear the IT pending Bit */\r
- TIMx->SR = (uint16_t)~TIM_IT;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx\92s DMA interface.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_DMABase: DMA Base address.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,\r
- * TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,\r
- * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,\r
- * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,\r
- * TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, \r
- * TIM_DMABase_CCR4, TIM_DMABase_DCR.\r
- * @param TIM_DMABurstLength: DMA Burst length.\r
- * This parameter can be one value between:\r
- * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.\r
- * @retval None\r
- */\r
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); \r
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));\r
- /* Set the DMA Base and the DMA Burst Length */\r
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx\92s DMA Requests.\r
- * @param TIMx: where x can be 2, 3, 4, 6 or 7 to select the TIM peripheral. \r
- * @param TIM_DMASource: specifies the DMA Request sources.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_DMA_Update: TIM update Interrupt source\r
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source\r
- * @param NewState: new state of the DMA Request sources.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the DMA sources */\r
- TIMx->DIER |= TIM_DMASource; \r
- }\r
- else\r
- {\r
- /* Disable the DMA sources */\r
- TIMx->DIER &= (uint16_t)~TIM_DMASource;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx peripheral Capture Compare DMA source.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param NewState: new state of the Capture Compare DMA source\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Set the CCDS Bit */\r
- TIMx->CR2 |= TIM_CR2_CCDS;\r
- }\r
- else\r
- {\r
- /* Reset the CCDS Bit */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group5 Clocks management functions\r
- * @brief Clocks management functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Clocks management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the TIMx internal Clock\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- /* Disable slave mode to clock the prescaler directly with the internal clock */\r
- TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Internal Trigger as External Clock\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_ITRSource: Trigger source.\r
- * This parameter can be one of the following values:\r
- * @param TIM_TS_ITR0: Internal Trigger 0\r
- * @param TIM_TS_ITR1: Internal Trigger 1\r
- * @param TIM_TS_ITR2: Internal Trigger 2\r
- * @param TIM_TS_ITR3: Internal Trigger 3\r
- * @retval None\r
- */\r
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
- /* Select the Internal Trigger */\r
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);\r
- /* Select the External clock mode1 */\r
- TIMx->SMCR |= TIM_SlaveMode_External1;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Trigger as External Clock\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_TIxExternalCLKSource: Trigger source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector\r
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1\r
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2\r
- * @param TIM_ICPolarity: specifies the TIx Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param ICFilter : specifies the filter value.\r
- * This parameter must be a value between 0x0 and 0xF.\r
- * @retval None\r
- */\r
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
- uint16_t TIM_ICPolarity, uint16_t ICFilter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));\r
- assert_param(IS_TIM_IC_FILTER(ICFilter));\r
- \r
- /* Configure the Timer Input Clock Source */\r
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)\r
- {\r
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
- }\r
- else\r
- {\r
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
- }\r
- /* Select the Trigger source */\r
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);\r
- /* Select the External clock mode1 */\r
- TIMx->SMCR |= TIM_SlaveMode_External1;\r
-}\r
-\r
-/**\r
- * @brief Configures the External clock Mode1\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
- * @param ExtTRGFilter: External Trigger Filter.\r
- * This parameter must be a value between 0x00 and 0x0F\r
- * @retval None\r
- */\r
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
- \r
- /* Configure the ETR Clock source */\r
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
- \r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = TIMx->SMCR;\r
- /* Reset the SMS Bits */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
- /* Select the External clock mode1 */\r
- tmpsmcr |= TIM_SlaveMode_External1;\r
- /* Select the Trigger selection : ETRF */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
- tmpsmcr |= TIM_TS_ETRF;\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
- * @brief Configures the External clock Mode2\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
- * @param ExtTRGFilter: External Trigger Filter.\r
- * This parameter must be a value between 0x00 and 0x0F\r
- * @retval None\r
- */\r
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
- \r
- /* Configure the ETR Clock source */\r
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
- /* Enable the External clock mode2 */\r
- TIMx->SMCR |= TIM_SMCR_ECE;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group6 Synchronization management functions\r
- * @brief Synchronization management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Synchronization management functions\r
- =============================================================================== \r
- \r
- =================================================================== \r
- TIM Driver: how to use it in synchronization Mode\r
- =================================================================== \r
- Case of two/several Timers\r
- **************************\r
- 1. Configure the Master Timers using the following functions:\r
- - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); \r
- - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); \r
- 2. Configure the Slave Timers using the following functions: \r
- - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); \r
- - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); \r
- \r
- Case of Timers and external trigger(ETR pin)\r
- ******************************************** \r
- 1. Configure the Etrenal trigger using this function:\r
- - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter);\r
- 2. Configure the Slave Timers using the following functions: \r
- - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); \r
- - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Selects the Input Trigger source\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_InputTriggerSource: The Input Trigger source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_TS_ITR0: Internal Trigger 0\r
- * @arg TIM_TS_ITR1: Internal Trigger 1\r
- * @arg TIM_TS_ITR2: Internal Trigger 2\r
- * @arg TIM_TS_ITR3: Internal Trigger 3\r
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
- * @arg TIM_TS_ETRF: External Trigger input\r
- * @retval None\r
- */\r
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
-{\r
- uint16_t tmpsmcr = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx)); \r
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
-\r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = TIMx->SMCR;\r
- /* Reset the TS Bits */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
- /* Set the Input Trigger source */\r
- tmpsmcr |= TIM_InputTriggerSource;\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx Trigger Output Mode.\r
- * @param TIMx: where x can be 2, 3, 4, 6, 7 or 9 to select the TIM peripheral.\r
- * @param TIM_TRGOSource: specifies the Trigger Output source.\r
- * This paramter can be one of the following values:\r
- *\r
- * - For all TIMx\r
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).\r
- *\r
- * - For all TIMx except TIM6 and TIM7\r
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag\r
- * is to be set, as soon as a capture or compare match occurs (TRGO).\r
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).\r
-\r
- * - For all TIMx except TIM6, TIM7, TIM10 and TIM11\r
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).\r
-\r
- * - For TIM2, TIM3 and TIM4\r
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).\r
- *\r
- * @retval None\r
- */\r
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));\r
-\r
- /* Reset the MMS Bits */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);\r
- /* Select the TRGO source */\r
- TIMx->CR2 |= TIM_TRGOSource;\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx Slave Mode.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.\r
- * This paramter can be one of the following values:\r
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes\r
- * the counter and triggers an update of the registers.\r
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.\r
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.\r
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.\r
- * @retval None\r
- */\r
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx)); \r
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));\r
- \r
- /* Reset the SMS Bits */\r
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);\r
- /* Select the Slave Mode */\r
- TIMx->SMCR |= TIM_SlaveMode;\r
-}\r
-\r
-/**\r
- * @brief Sets or Resets the TIMx Master/Slave Mode.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.\r
- * This paramter can be one of the following values:\r
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer\r
- * and its slaves (through TRGO).\r
- * @arg TIM_MasterSlaveMode_Disable: No action\r
- * @retval None\r
- */\r
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));\r
- \r
- /* Reset the MSM Bit */\r
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);\r
- \r
- /* Set or Reset the MSM Bit */\r
- TIMx->SMCR |= TIM_MasterSlaveMode;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx External Trigger (ETR).\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
- * @param ExtTRGFilter: External Trigger Filter.\r
- * This parameter must be a value between 0x00 and 0x0F\r
- * @retval None\r
- */\r
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
- \r
- tmpsmcr = TIMx->SMCR;\r
- /* Reset the ETR Bits */\r
- tmpsmcr &= SMCR_ETR_MASK;\r
- /* Set the Prescaler, the Filter value and the Polarity */\r
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group7 Specific interface management functions\r
- * @brief Specific interface management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Specific interface management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the TIMx Encoder Interface.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.\r
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.\r
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending\r
- * on the level of the other input.\r
- * @param TIM_IC1Polarity: specifies the IC1 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
- * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
- * @param TIM_IC2Polarity: specifies the IC2 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
- * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
- * @retval None\r
- */\r
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- uint16_t tmpccmr1 = 0;\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));\r
- \r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = TIMx->SMCR;\r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- /* Set the encoder Mode */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
- tmpsmcr |= TIM_EncoderMode;\r
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));\r
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;\r
- /* Set the TI1 and the TI2 Polarities */\r
- tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));\r
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmr1;\r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx\92s Hall sensor interface.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param NewState: new state of the TIMx Hall sensor interface.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Set the TI1S Bit */\r
- TIMx->CR2 |= TIM_CR2_TI1S;\r
- }\r
- else\r
- {\r
- /* Reset the TI1S Bit */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Group8 Specific remapping management function\r
- * @brief Specific remapping management function\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Specific remapping management function\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the TIM9, TIM10 and TIM11 Remapping input Capabilities.\r
- * @param TIMx: where x can be 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_Remap: specifies the TIM input remapping source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default)\r
- * @arg TIM9_LSE: TIM9 Channel 1 is connected to LSE clock.\r
- * @arg TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default) \r
- * @arg TIM10_LSI: TIM10 Channel 1 is connected to LSI clock.\r
- * @arg TIM10_LSE: TIM10 Channel 1 is connected to LSE clock.\r
- * @arg TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event. \r
- * @arg TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default) \r
- * @arg TIM11_MSI: TIM11 Channel 1 is connected to MSI clock.\r
- * @arg TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock. \r
- * @retval None\r
- */\r
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_REMAP(TIM_Remap));\r
-\r
- /* Set the Timer remapping configuration */\r
- TIMx->OR = TIM_Remap;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @brief Configure the TI1 as Input.\r
- * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr1 = 0, tmpccer = 0;\r
- \r
- /* Disable the Channel 1: Reset the CC1E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);\r
- tmpccmr1 = TIMx->CCMR1;\r
- tmpccer = TIMx->CCER;\r
- /* Select the Input and set the filter */\r
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));\r
- tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
- /* Select the Polarity and set the CC1E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
- /* Write to TIMx CCMR1 and CCER registers */\r
- TIMx->CCMR1 = tmpccmr1;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI2 as Input.\r
- * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;\r
- \r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);\r
- tmpccmr1 = TIMx->CCMR1;\r
- tmpccer = TIMx->CCER;\r
- tmp = (uint16_t)(TIM_ICPolarity << 4);\r
- /* Select the Input and set the filter */\r
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));\r
- tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);\r
- tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);\r
- /* Select the Polarity and set the CC2E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);\r
- /* Write to TIMx CCMR1 and CCER registers */\r
- TIMx->CCMR1 = tmpccmr1 ;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI3 as Input.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
- \r
- /* Disable the Channel 3: Reset the CC3E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);\r
- tmpccmr2 = TIMx->CCMR2;\r
- tmpccer = TIMx->CCER;\r
- tmp = (uint16_t)(TIM_ICPolarity << 8);\r
- /* Select the Input and set the filter */\r
- tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));\r
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
- /* Select the Polarity and set the CC3E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);\r
- /* Write to TIMx CCMR2 and CCER registers */\r
- TIMx->CCMR2 = tmpccmr2;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI4 as Input.\r
- * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
- \r
- /* Disable the Channel 4: Reset the CC4E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);\r
- tmpccmr2 = TIMx->CCMR2;\r
- tmpccer = TIMx->CCER;\r
- tmp = (uint16_t)(TIM_ICPolarity << 12);\r
- /* Select the Input and set the filter */\r
- tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));\r
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);\r
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);\r
-\r
- /* Select the Polarity and set the CC4E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));\r
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);\r
- /* Write to TIMx CCMR2 and CCER registers */\r
- TIMx->CCMR2 = tmpccmr2;\r
- TIMx->CCER = tmpccer ;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff