+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_rcc.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Reset and clock control (RCC) peripheral: \r
- * - Internal/external clocks, PLL, CSS and MCO configuration\r
- * - System, AHB and APB busses clocks configuration\r
- * - Peripheral clocks configuration\r
- * - Interrupts and flags management\r
- *\r
- * @verbatim\r
- * \r
- * ===================================================================\r
- * RCC specific features\r
- * ===================================================================\r
- * \r
- * After reset the device is running from MSI (2 MHz) with Flash 0 WS, \r
- * all peripherals are off except internal SRAM, Flash and JTAG.\r
- * - There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r
- * all peripherals mapped on these busses are running at MSI speed.\r
- * - The clock for all peripherals is switched off, except the SRAM and FLASH.\r
- * - All GPIOs are in input floating state, except the JTAG pins which\r
- * are assigned to be used for debug purpose.\r
- * \r
- * Once the device started from reset, the user application has to: \r
- * - Configure the clock source to be used to drive the System clock\r
- * (if the application needs higher frequency/performance)\r
- * - Configure the System clock frequency and Flash settings \r
- * - Configure the AHB and APB busses prescalers\r
- * - Enable the clock for the peripheral(s) to be used\r
- * - Configure the clock source(s) for peripherals whose clocks are not\r
- * derived from the System clock (ADC, RTC/LCD and IWDG) \r
- * \r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC \r
- * @brief RCC driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/* ------------ RCC registers bit address in the alias region ----------- */\r
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
-\r
-/* --- CR Register ---*/\r
-\r
-/* Alias word address of HSION bit */\r
-#define CR_OFFSET (RCC_OFFSET + 0x00)\r
-#define HSION_BitNumber 0x00\r
-#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
-\r
-/* Alias word address of MSION bit */\r
-#define MSION_BitNumber 0x08\r
-#define CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))\r
-\r
-/* Alias word address of PLLON bit */\r
-#define PLLON_BitNumber 0x18\r
-#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
-\r
-/* Alias word address of CSSON bit */\r
-#define CSSON_BitNumber 0x1C\r
-#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
-\r
-/* --- CSR Register ---*/\r
-\r
-/* Alias word address of LSION bit */\r
-#define CSR_OFFSET (RCC_OFFSET + 0x34)\r
-#define LSION_BitNumber 0x00\r
-#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
-\r
-/* Alias word address of RTCEN bit */\r
-#define RTCEN_BitNumber 0x16\r
-#define CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
-\r
-/* Alias word address of RTCRST bit */\r
-#define RTCRST_BitNumber 0x17\r
-#define CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))\r
-\r
-\r
-/* ---------------------- RCC registers mask -------------------------------- */\r
-/* RCC Flag Mask */\r
-#define FLAG_MASK ((uint8_t)0x1F)\r
-\r
-/* CR register byte 3 (Bits[23:16]) base address */\r
-#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)\r
-\r
-/* ICSCR register byte 4 (Bits[31:24]) base address */\r
-#define ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)\r
-\r
-/* CFGR register byte 3 (Bits[23:16]) base address */\r
-#define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)\r
-\r
-/* CFGR register byte 4 (Bits[31:24]) base address */\r
-#define CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)\r
-\r
-/* CIR register byte 2 (Bits[15:8]) base address */\r
-#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)\r
-\r
-/* CIR register byte 3 (Bits[23:16]) base address */\r
-#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)\r
-\r
-/* CSR register byte 2 (Bits[15:8]) base address */\r
-#define CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-\r
-static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\r
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup RCC_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions\r
- * @brief Internal and external clocks, PLL, CSS and MCO configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Internal/external clocks, PLL, CSS and MCO configuration functions\r
- =============================================================================== \r
-\r
- This section provide functions allowing to configure the internal/external clocks,\r
- PLL, CSS and MCO.\r
- \r
- 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through\r
- the PLL as System clock source.\r
-\r
- 2. MSI (multi-speed internal), multispeed low power RC (65.536 KHz to 4.194 MHz)\r
- MHz used as System clock source.\r
-\r
- 3. LSI (low-speed internal), 37 KHz low consumption RC used as IWDG and/or RTC\r
- clock source.\r
-\r
- 4. HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or\r
- through the PLL as System clock source. Can be used also as RTC clock source.\r
-\r
- 5. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. \r
-\r
- 6. PLL (clocked by HSI or HSE), for System clock and USB (48 MHz).\r
-\r
- 7. CSS (Clock security system), once enable and if a HSE clock failure occurs \r
- (HSE used directly or through PLL as System clock source), the System clock\r
- is automatically switched to MSI and an interrupt is generated if enabled. \r
- The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) \r
- exception vector. \r
-\r
- 8. MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI, HSE, PLL,\r
- LSI or LSE clock (through a configurable prescaler) on PA8 pin.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Resets the RCC clock configuration to the default reset state.\r
- * @note - The default reset state of the clock configuration is given below:\r
- * - MSI ON and used as system clock source (MSI range is not modified\r
- * by this function, it keep the value configured by user application)\r
- * - HSI, HSE and PLL OFF\r
- * - AHB, APB1 and APB2 prescaler set to 1.\r
- * - CSS and MCO OFF\r
- * - All interrupts disabled\r
- * - However, this function doesn't modify the configuration of the\r
- * - Peripheral clocks\r
- * - LSI, LSE and RTC clocks \r
- * @param None\r
- * @retval None\r
- */\r
-void RCC_DeInit(void)\r
-{\r
- \r
- /* Set MSION bit */\r
- RCC->CR |= (uint32_t)0x00000100;\r
-\r
- /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
- RCC->CFGR &= (uint32_t)0x88FFC00C;\r
- \r
- /* Reset HSION, HSEON, CSSON and PLLON bits */\r
- RCC->CR &= (uint32_t)0xEEFEFFFE;\r
-\r
- /* Reset HSEBYP bit */\r
- RCC->CR &= (uint32_t)0xFFFBFFFF;\r
-\r
- /* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
- RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
-\r
- /* Disable all interrupts */\r
- RCC->CIR = 0x00000000;\r
-}\r
-\r
-/**\r
- * @brief Configures the External High Speed oscillator (HSE).\r
- * @note - After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
- * software should wait on HSERDY flag to be set indicating that HSE clock\r
- * is stable and can be used to clock the PLL and/or system clock.\r
- * - HSE state can not be changed if it is used directly or through the\r
- * PLL as system clock. In this case, you have to select another source\r
- * of the system clock then change the HSE state (ex. disable it).\r
- * - The HSE is stopped by hardware when entering STOP and STANDBY modes. \r
- * @note This function reset the CSSON bit, so if the Clock security system(CSS)\r
- * was previously enabled you have to enable it again after calling this\r
- * function.\r
- * @param RCC_HSE: specifies the new state of the HSE.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r
- * 6 HSE oscillator clock cycles.\r
- * @arg RCC_HSE_ON: turn ON the HSE oscillator\r
- * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r
- * @retval None\r
- */\r
-void RCC_HSEConfig(uint8_t RCC_HSE)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_HSE(RCC_HSE));\r
-\r
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;\r
-\r
- /* Set the new HSE configuration -------------------------------------------*/\r
- *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;\r
-\r
-}\r
-\r
-/**\r
- * @brief Waits for HSE start-up.\r
- * @note This functions waits on HSERDY flag to be set and return SUCCESS if \r
- * this flag is set, otherwise returns ERROR if the timeout is reached \r
- * and this flag is not set. The timeout value is defined by the constant\r
- * HSE_STARTUP_TIMEOUT in stm32l1xx.h file. You can tailor it depending\r
- * on the HSE crystal used in your application. \r
- * @param None\r
- * @retval An ErrorStatus enumeration value:\r
- * - SUCCESS: HSE oscillator is stable and ready to use\r
- * - ERROR: HSE oscillator not yet ready\r
- */\r
-ErrorStatus RCC_WaitForHSEStartUp(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0;\r
- ErrorStatus status = ERROR;\r
- FlagStatus HSEStatus = RESET;\r
- \r
- /* Wait till HSE is ready and if timeout is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
- StartUpCounter++; \r
- } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));\r
- \r
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
- {\r
- status = SUCCESS;\r
- }\r
- else\r
- {\r
- status = ERROR;\r
- } \r
- return (status);\r
-}\r
-\r
-/**\r
- * @brief Adjusts the Internal Multi Speed oscillator (MSI) calibration value.\r
- * @note The calibration is used to compensate for the variations in voltage\r
- * and temperature that influence the frequency of the internal MSI RC.\r
- * Refer to the Application Note AN3300 for more details on how to \r
- * calibrate the MSI.\r
- * @param MSICalibrationValue: specifies the MSI calibration trimming value.\r
- * This parameter must be a number between 0 and 0xFF.\r
- * @retval None\r
- */\r
-void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)\r
-{\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));\r
-\r
- *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue; \r
-}\r
-\r
-/**\r
- * @brief Configures the Internal Multi Speed oscillator (MSI) clock range.\r
- * @note - After restart from Reset or wakeup from STANDBY, the MSI clock is \r
- * around 2.097 MHz. The MSI clock does not change after wake-up from\r
- * STOP mode.\r
- * - The MSI clock range can be modified on the fly. \r
- * @param RCC_MSIRange: specifies the MSI Clock range.\r
- * This parameter must be one of the following values:\r
- * @arg RCC_MSIRange_0: MSI clock is around 65.536 KHz\r
- * @arg RCC_MSIRange_1: MSI clock is around 131.072 KHz\r
- * @arg RCC_MSIRange_2: MSI clock is around 262.144 KHz\r
- * @arg RCC_MSIRange_3: MSI clock is around 524.288 KHz\r
- * @arg RCC_MSIRange_4: MSI clock is around 1.048 MHz\r
- * @arg RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)\r
- * @arg RCC_MSIRange_6: MSI clock is around \r
- * \r
- * @retval None\r
- */\r
-void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));\r
- \r
- tmpreg = RCC->ICSCR;\r
- \r
- /* Clear MSIRANGE[2:0] bits */\r
- tmpreg &= ~RCC_ICSCR_MSIRANGE;\r
- \r
- /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */\r
- tmpreg |= (uint32_t)RCC_MSIRange;\r
-\r
- /* Store the new value */\r
- RCC->ICSCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Internal Multi Speed oscillator (MSI).\r
- * @note - The MSI is stopped by hardware when entering STOP and STANDBY modes.\r
- * It is used (enabled by hardware) as system clock source after\r
- * startup from Reset, wakeup from STOP and STANDBY mode, or in case\r
- * of failure of the HSE used directly or indirectly as system clock\r
- * (if the Clock Security System CSS is enabled). \r
- * - MSI can not be stopped if it is used as system clock source.\r
- * In this case, you have to select another source of the system\r
- * clock then stop the MSI. \r
- * - After enabling the MSI, the application software should wait on\r
- * MSIRDY flag to be set indicating that MSI clock is stable and can\r
- * be used as system clock source. \r
- * @param NewState: new state of the MSI.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator\r
- * clock cycles. \r
- * @retval None\r
- */\r
-void RCC_MSICmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
- * @note The calibration is used to compensate for the variations in voltage\r
- * and temperature that influence the frequency of the internal HSI RC.\r
- * Refer to the Application Note AN3300 for more details on how to \r
- * calibrate the HSI.\r
- * @param HSICalibrationValue: specifies the HSI calibration trimming value.\r
- * This parameter must be a number between 0 and 0x1F.\r
- * @retval None\r
- */\r
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));\r
- \r
- tmpreg = RCC->ICSCR;\r
- \r
- /* Clear HSITRIM[4:0] bits */\r
- tmpreg &= ~RCC_ICSCR_HSITRIM;\r
- \r
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
- tmpreg |= (uint32_t)HSICalibrationValue << 8;\r
-\r
- /* Store the new value */\r
- RCC->ICSCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Internal High Speed oscillator (HSI).\r
- * @note - After enabling the HSI, the application software should wait on \r
- * HSIRDY flag to be set indicating that HSI clock is stable and can\r
- * be used to clock the PLL and/or system clock.\r
- * - HSI can not be stopped if it is used directly or through the PLL\r
- * as system clock. In this case, you have to select another source \r
- * of the system clock then stop the HSI.\r
- * - The HSI is stopped by hardware when entering STOP and STANDBY modes. \r
- * @param NewState: new state of the HSI.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
- * clock cycles. \r
- * @retval None\r
- */\r
-void RCC_HSICmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Configures the External Low Speed oscillator (LSE).\r
- * @note - As the LSE is in the RTC domain and write access is denied to this\r
- * domain after reset, you have to enable write access using \r
- * PWR_RTCAccessCmd(ENABLE) function before to configure the LSE\r
- * (to be done once after reset). \r
- * - After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application\r
- * software should wait on LSERDY flag to be set indicating that LSE clock\r
- * is stable and can be used to clock the RTC.\r
- * @param RCC_LSE: specifies the new state of the LSE.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r
- * 6 LSE oscillator clock cycles.\r
- * @arg RCC_LSE_ON: turn ON the LSE oscillator\r
- * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r
- * @retval None\r
- */\r
-void RCC_LSEConfig(uint8_t RCC_LSE)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_LSE(RCC_LSE));\r
- \r
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
- *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;\r
-\r
- /* Set the new LSE configuration -------------------------------------------*/\r
- *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE; \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Internal Low Speed oscillator (LSI). \r
- * @note - After enabling the LSI, the application software should wait on \r
- * LSIRDY flag to be set indicating that LSI clock is stable and can\r
- * be used to clock the IWDG and/or the RTC.\r
- * - LSI can not be disabled if the IWDG is running. \r
- * @param NewState: new state of the LSI.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
- * clock cycles. \r
- * @retval None\r
- */\r
-void RCC_LSICmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Configures the PLL clock source and multiplication factor.\r
- * @note This function must be used only when the PLL is disabled.\r
- * \r
- * @param RCC_PLLSource: specifies the PLL entry clock source.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source\r
- * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source\r
- * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as\r
- * PLL source).\r
- * \r
- * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock\r
- * This parameter can be:\r
- * @arg RCC_PLLMul_3: PLL clock source multiplied by 3\r
- * @arg RCC_PLLMul_4: PLL clock source multiplied by 4\r
- * @arg RCC_PLLMul_6: PLL clock source multiplied by 6\r
- * @arg RCC_PLLMul_8: PLL clock source multiplied by 8\r
- * @arg RCC_PLLMul_12: PLL clock source multiplied by 12\r
- * @arg RCC_PLLMul_16: PLL clock source multiplied by 16 \r
- * @arg RCC_PLLMul_24: PLL clock source multiplied by 24\r
- * @arg RCC_PLLMul_32: PLL clock source multiplied by 32\r
- * @arg RCC_PLLMul_48: PLL clock source multiplied by 48\r
- * @note The application software must set correctly the PLL multiplication\r
- * factor to avoid exceeding\r
- * - 96 MHz as PLLVCO when the product is in range 1\r
- * - 48 MHz as PLLVCO when the product is in range 2\r
- * - 24 MHz when the product is in range 3\r
- * @note When using the USB the PLLVCO should be 96MHz\r
- * \r
- * @param RCC_PLLDiv: specifies the PLL division factor.\r
- * This parameter can be:\r
- * @arg RCC_PLLDiv_2: PLL Clock output divided by 2 \r
- * @arg RCC_PLLDiv_3: PLL Clock output divided by 3 \r
- * @arg RCC_PLLDiv_4: PLL Clock output divided by 4 \r
- * @note The application software must set correctly the output division to avoid\r
- * exceeding 32 MHz as SYSCLK.\r
- * \r
- * @retval None\r
- */\r
-void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
- assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
- assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));\r
- \r
- *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the PLL.\r
- * @note - After enabling the PLL, the application software should wait on \r
- * PLLRDY flag to be set indicating that PLL clock is stable and can\r
- * be used as system clock source.\r
- * - The PLL can not be disabled if it is used as system clock source\r
- * - The PLL is disabled by hardware when entering STOP and STANDBY modes. \r
- * @param NewState: new state of the PLL.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_PLLCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Clock Security System.\r
- * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
- * is automatically disabled and an interrupt is generated to inform the\r
- * software about the failure (Clock Security System Interrupt, CSSI),\r
- * allowing the MCU to perform rescue operations. The CSSI is linked to \r
- * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. \r
- * @param NewState: new state of the Clock Security System.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Selects the clock source to output on MCO pin (PA8).\r
- * @note PA8 should be configured in alternate function mode. \r
- * @param RCC_MCOSource: specifies the clock source to output.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_MCOSource_NoClock: No clock selected\r
- * @arg RCC_MCOSource_SYSCLK: System clock selected\r
- * @arg RCC_MCOSource_HSI: HSI oscillator clock selected\r
- * @arg RCC_MCOSource_MSI: MSI oscillator clock selected \r
- * @arg RCC_MCOSource_HSE: HSE oscillator clock selected\r
- * @arg RCC_MCOSource_PLLCLK: PLL clock selected\r
- * @arg RCC_MCOSource_LSI: LSI clock selected\r
- * @arg RCC_MCOSource_LSE: LSE clock selected \r
- * @param RCC_MCODiv: specifies the MCO prescaler.\r
- * This parameter can be one of the following values: \r
- * @arg RCC_MCODiv_1: no division applied to MCO clock \r
- * @arg RCC_MCODiv_2: division by 2 applied to MCO clock\r
- * @arg RCC_MCODiv_4: division by 4 applied to MCO clock\r
- * @arg RCC_MCODiv_8: division by 8 applied to MCO clock\r
- * @arg RCC_MCODiv_16: division by 16 applied to MCO clock \r
- * @retval None\r
- */\r
-void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));\r
- assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));\r
- \r
- /* Select MCO clock source and prescaler */\r
- *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCOSource | RCC_MCODiv; \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions\r
- * @brief System, AHB and APB busses clocks configuration functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- System, AHB and APB busses clocks configuration functions\r
- =============================================================================== \r
-\r
- This section provide functions allowing to configure the System, AHB, APB1 and \r
- APB2 busses clocks.\r
- \r
- 1. Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,\r
- HSE and PLL.\r
- The AHB clock (HCLK) is derived from System clock through configurable prescaler\r
- and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).\r
- APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through \r
- configurable prescalers and used to clock the peripherals mapped on these busses.\r
- You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. \r
-\r
-Note: All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
-==== - The USB 48 MHz clock which is derived from the PLL VCO clock.\r
- - The ADC clock which is always the HSI clock. A divider by 1, 2 or 4 allows\r
- to adapt the clock frequency to the device operating conditions. \r
- - The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE\r
- divided by a programmable prescaler).\r
- The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD\r
- clock frequency.\r
- - IWDG clock which is always the LSI clock.\r
- \r
- 2. The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32 MHz.\r
- Depending on the device voltage range, the maximum frequency should be \r
- adapted accordingly:\r
- +----------------------------------------------------------------+ \r
- | Wait states | HCLK clock frequency (MHz) |\r
- | |------------------------------------------------| \r
- | (Latency) | voltage range | voltage range | \r
- | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
- | |----------------|---------------|---------------| \r
- | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
- |-------------- |----------------|---------------|---------------| \r
- |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
- |---------------|----------------|---------------|---------------| \r
- |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| \r
- +----------------------------------------------------------------+ \r
-\r
- 3. After reset, the System clock source is the MSI (2 MHz) with 0 WS, Flash\r
- 32-bit access is enabled and prefetch is disabled.\r
- \r
- It is recommended to use the following software sequences to tune the number\r
- of wait states needed to access the Flash memory with the CPU frequency (HCLK).\r
- - Increasing the CPU frequency (in the same voltage range)\r
- - Program the Flash 64-bit access, using "FLASH_ReadAccess64Cmd(ENABLE)" function\r
- - Check that 64-bit access is taken into account by reading FLASH_ACR\r
- - Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function\r
- - Check that the new number of WS is taken into account by reading FLASH_ACR\r
- - Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
- - If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function\r
- - Check that the new CPU clock source is taken into account by reading \r
- the clock source status, using "RCC_GetSYSCLKSource()" function \r
- - Decreasing the CPU frequency (in the same voltage range)\r
- - Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
- - If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function\r
- - Check that the new CPU clock source is taken into account by reading \r
- the clock source status, using "RCC_GetSYSCLKSource()" function\r
- - Program the new number of WS, using "FLASH_SetLatency()" function\r
- - Check that the new number of WS is taken into account by reading FLASH_ACR\r
- - Enable the Flash 32-bit access, using "FLASH_ReadAccess64Cmd(DISABLE)" function\r
- - Check that 32-bit access is taken into account by reading FLASH_ACR\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the system clock (SYSCLK).\r
- * @note - The MSI is used (enabled by hardware) as system clock source after\r
- * startup from Reset, wake-up from STOP and STANDBY mode, or in case\r
- * of failure of the HSE used directly or indirectly as system clock\r
- * (if the Clock Security System CSS is enabled).\r
- * - A switch from one clock source to another occurs only if the target\r
- * clock source is ready (clock stable after startup delay or PLL locked). \r
- * If a clock source which is not yet ready is selected, the switch will\r
- * occur when the clock source will be ready. \r
- * You can use RCC_GetSYSCLKSource() function to know which clock is\r
- * currently used as system clock source. \r
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock source \r
- * This parameter can be one of the following values:\r
- * @arg RCC_SYSCLKSource_MSI: MSI selected as system clock source\r
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source\r
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source\r
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source\r
- * @retval None\r
- */\r
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
- \r
- tmpreg = RCC->CFGR;\r
- \r
- /* Clear SW[1:0] bits */\r
- tmpreg &= ~RCC_CFGR_SW;\r
- \r
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
- tmpreg |= RCC_SYSCLKSource;\r
- \r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Returns the clock source used as system clock.\r
- * @param None\r
- * @retval The clock source used as system clock. The returned value can be one \r
- * of the following values:\r
- * - 0x00: MSI used as system clock\r
- * - 0x04: HSI used as system clock \r
- * - 0x08: HSE used as system clock\r
- * - 0x0C: PLL used as system clock\r
- */\r
-uint8_t RCC_GetSYSCLKSource(void)\r
-{\r
- return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));\r
-}\r
-\r
-/**\r
- * @brief Configures the AHB clock (HCLK).\r
- * @note Depending on the device voltage range, the software has to set correctly\r
- * these bits to ensure that the system frequency does not exceed the\r
- * maximum allowed frequency (for more details refer to section above\r
- * "CPU, AHB and APB busses clocks configuration functions")\r
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
- * the system clock (SYSCLK).\r
- * This parameter can be one of the following values:\r
- * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
- * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r
- * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r
- * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r
- * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r
- * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r
- * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
- * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
- * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
- * @retval None\r
- */\r
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
- \r
- tmpreg = RCC->CFGR;\r
- \r
- /* Clear HPRE[3:0] bits */\r
- tmpreg &= ~RCC_CFGR_HPRE;\r
- \r
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
- tmpreg |= RCC_SYSCLK;\r
- \r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the Low Speed APB clock (PCLK1).\r
- * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r
- * the AHB clock (HCLK).\r
- * This parameter can be one of the following values:\r
- * @arg RCC_HCLK_Div1: APB1 clock = HCLK\r
- * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2\r
- * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4\r
- * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8\r
- * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16\r
- * @retval None\r
- */\r
-void RCC_PCLK1Config(uint32_t RCC_HCLK)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_PCLK(RCC_HCLK));\r
- \r
- tmpreg = RCC->CFGR;\r
- \r
- /* Clear PPRE1[2:0] bits */\r
- tmpreg &= ~RCC_CFGR_PPRE1;\r
- \r
- /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
- tmpreg |= RCC_HCLK;\r
- \r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the High Speed APB clock (PCLK2).\r
- * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r
- * the AHB clock (HCLK).\r
- * This parameter can be one of the following values:\r
- * @arg RCC_HCLK_Div1: APB2 clock = HCLK\r
- * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2\r
- * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4\r
- * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8\r
- * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16\r
- * @retval None\r
- */\r
-void RCC_PCLK2Config(uint32_t RCC_HCLK)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RCC_PCLK(RCC_HCLK));\r
- \r
- tmpreg = RCC->CFGR;\r
- \r
- /* Clear PPRE2[2:0] bits */\r
- tmpreg &= ~RCC_CFGR_PPRE2;\r
- \r
- /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
- tmpreg |= RCC_HCLK << 3;\r
- \r
- /* Store the new value */\r
- RCC->CFGR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Returns the frequencies of the System, AHB and APB busses clocks.\r
- * @note - The frequency returned by this function is not the real frequency\r
- * in the chip. It is calculated based on the predefined constant and\r
- * the source selected by RCC_SYSCLKConfig():\r
- * \r
- * - If SYSCLK source is MSI, function returns constant the MSI value\r
- * as defined by the MSI range, refer to RCC_MSIRangeConfig()\r
- * \r
- * - If SYSCLK source is HSI, function returns constant HSI_VALUE(*)\r
- * \r
- * - If SYSCLK source is HSE, function returns constant HSE_VALUE(**)\r
- * \r
- * - If SYSCLK source is PLL, function returns constant HSE_VALUE(**) \r
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
- * \r
- * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value\r
- * 16 MHz) but the real value may vary depending on the variations\r
- * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). \r
- * \r
- * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value\r
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
- * frequency of the crystal used. Otherwise, this function may\r
- * return wrong result.\r
- * \r
- * - The result of this function could be not correct when using fractional\r
- * value for HSE crystal. \r
- * \r
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold \r
- * the clocks frequencies. \r
- * @retval None\r
- */\r
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
-{\r
- uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0;\r
-\r
- /* Get SYSCLK source -------------------------------------------------------*/\r
- tmp = RCC->CFGR & RCC_CFGR_SWS;\r
- \r
- switch (tmp)\r
- {\r
- case 0x00: /* MSI used as system clock */\r
- msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;\r
- RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));\r
- break;\r
- case 0x04: /* HSI used as system clock */\r
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
- break;\r
- case 0x08: /* HSE used as system clock */\r
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;\r
- break;\r
- case 0x0C: /* PLL used as system clock */\r
- /* Get PLL clock source and multiplication factor ----------------------*/\r
- pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
- plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
- pllmul = PLLMulTable[(pllmul >> 18)];\r
- plldiv = (plldiv >> 22) + 1;\r
- \r
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
-\r
- if (pllsource == 0x00)\r
- {\r
- /* HSI oscillator clock selected as PLL clock source */\r
- RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv);\r
- }\r
- else\r
- {\r
- /* HSE selected as PLL clock source */\r
- RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv);\r
- }\r
- break;\r
- default: /* MSI used as system clock */\r
- msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;\r
- RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1)));\r
- break;\r
- }\r
- /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/\r
- /* Get HCLK prescaler */\r
- tmp = RCC->CFGR & RCC_CFGR_HPRE;\r
- tmp = tmp >> 4;\r
- presc = APBAHBPrescTable[tmp]; \r
- /* HCLK clock frequency */\r
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
-\r
- /* Get PCLK1 prescaler */\r
- tmp = RCC->CFGR & RCC_CFGR_PPRE1;\r
- tmp = tmp >> 8;\r
- presc = APBAHBPrescTable[tmp];\r
- /* PCLK1 clock frequency */\r
- RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
-\r
- /* Get PCLK2 prescaler */\r
- tmp = RCC->CFGR & RCC_CFGR_PPRE2;\r
- tmp = tmp >> 11;\r
- presc = APBAHBPrescTable[tmp];\r
- /* PCLK2 clock frequency */\r
- RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Group3 Peripheral clocks configuration functions\r
- * @brief Peripheral clocks configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Peripheral clocks configuration functions\r
- =============================================================================== \r
-\r
- This section provide functions allowing to configure the Peripheral clocks. \r
- \r
- 1. The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE\r
- divided by a programmable prescaler).\r
- \r
- 2. After restart from Reset or wakeup from STANDBY, all peripherals are off\r
- except internal SRAM, Flash and JTAG. Before to start using a peripheral you\r
- have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd()\r
- , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.\r
-\r
- 3. To reset the peripherals configuration (to the default state after device reset)\r
- you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and \r
- RCC_APB1PeriphResetCmd() functions.\r
- \r
- 4. To further reduce power consumption in SLEEP mode the peripheral clocks can\r
- be disabled prior to executing the WFI or WFE instructions. You can do this\r
- using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and\r
- RCC_APB1PeriphClockLPModeCmd() functions. \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the RTC and LCD clock (RTCCLK / LCDCLK).\r
- * @note - As the RTC clock configuration bits are in the RTC domain and write\r
- * access is denied to this domain after reset, you have to enable write\r
- * access using PWR_RTCAccessCmd(ENABLE) function before to configure\r
- * the RTC clock source (to be done once after reset). \r
- * - Once the RTC clock is configured it can't be changed unless the RTC\r
- * is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)\r
- * - The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).\r
- * \r
- * @param RCC_RTCCLKSource: specifies the RTC clock source.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
- * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
- * @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock\r
- * @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock\r
- * @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock\r
- * @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock\r
- * \r
- * @note - If the LSE or LSI is used as RTC clock source, the RTC continues to\r
- * work in STOP and STANDBY modes, and can be used as wakeup source.\r
- * However, when the HSE clock is used as RTC clock source, the RTC\r
- * cannot be used in STOP and STANDBY modes.\r
- * \r
- * - The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
- * RTC clock source).\r
- * \r
- * @retval None\r
- */\r
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
- \r
- if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)\r
- { \r
- /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */\r
- tmpreg = RCC->CR;\r
-\r
- /* Clear RTCPRE[1:0] bits */\r
- tmpreg &= ~RCC_CR_RTCPRE;\r
-\r
- /* Configure HSE division factor for RTC clock */\r
- tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE);\r
-\r
- /* Store the new value */\r
- RCC->CR = tmpreg;\r
- }\r
- \r
- RCC->CSR &= ~RCC_CSR_RTCSEL;\r
- \r
- /* Select the RTC clock source */\r
- RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the RTC clock.\r
- * @note This function must be used only after the RTC clock source was selected\r
- * using the RCC_RTCCLKConfig function.\r
- * @param NewState: new state of the RTC clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_RTCCLKCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Forces or releases the RTC peripheral and associated resources reset.\r
- * @note This function resets the RTC peripheral, RTC clock source selection\r
- * (in RCC_CSR) and the backup registers.\r
- * @param NewState: new state of the RTC reset.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_RTCResetCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the AHB peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
- * using it. \r
- * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_AHBPeriph_GPIOA\r
- * @arg RCC_AHBPeriph_GPIOB\r
- * @arg RCC_AHBPeriph_GPIOC \r
- * @arg RCC_AHBPeriph_GPIOD\r
- * @arg RCC_AHBPeriph_GPIOE\r
- * @arg RCC_AHBPeriph_GPIOH\r
- * @arg RCC_AHBPeriph_CRC\r
- * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) \r
- * @arg RCC_AHBPeriph_DMA1\r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- RCC->AHBENR |= RCC_AHBPeriph;\r
- }\r
- else\r
- {\r
- RCC->AHBENR &= ~RCC_AHBPeriph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
- * using it.\r
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB2Periph_SYSCFG\r
- * @arg RCC_APB2Periph_TIM9\r
- * @arg RCC_APB2Periph_TIM10\r
- * @arg RCC_APB2Periph_TIM11\r
- * @arg RCC_APB2Periph_ADC1\r
- * @arg RCC_APB2Periph_SPI1\r
- * @arg RCC_APB2Periph_USART1 \r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB2ENR |= RCC_APB2Periph;\r
- }\r
- else\r
- {\r
- RCC->APB2ENR &= ~RCC_APB2Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r
- * @note After reset, the peripheral clock (used for registers read/write access)\r
- * is disabled and the application software has to enable this clock before \r
- * using it.\r
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB1Periph_TIM2\r
- * @arg RCC_APB1Periph_TIM3\r
- * @arg RCC_APB1Periph_TIM4\r
- * @arg RCC_APB1Periph_TIM6\r
- * @arg RCC_APB1Periph_TIM7\r
- * @arg RCC_APB1Periph_LCD\r
- * @arg RCC_APB1Periph_WWDG\r
- * @arg RCC_APB1Periph_SPI2\r
- * @arg RCC_APB1Periph_USART2\r
- * @arg RCC_APB1Periph_USART3\r
- * @arg RCC_APB1Periph_I2C1\r
- * @arg RCC_APB1Periph_I2C2\r
- * @arg RCC_APB1Periph_USB\r
- * @arg RCC_APB1Periph_PWR\r
- * @arg RCC_APB1Periph_DAC\r
- * @arg RCC_APB1Periph_COMP \r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB1ENR |= RCC_APB1Periph;\r
- }\r
- else\r
- {\r
- RCC->APB1ENR &= ~RCC_APB1Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Forces or releases AHB peripheral reset.\r
- * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_AHBPeriph_GPIOA\r
- * @arg RCC_AHBPeriph_GPIOB\r
- * @arg RCC_AHBPeriph_GPIOC \r
- * @arg RCC_AHBPeriph_GPIOD\r
- * @arg RCC_AHBPeriph_GPIOE\r
- * @arg RCC_AHBPeriph_GPIOH\r
- * @arg RCC_AHBPeriph_CRC\r
- * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) \r
- * @arg RCC_AHBPeriph_DMA1 \r
- * @param NewState: new state of the specified peripheral reset.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- RCC->AHBRSTR |= RCC_AHBPeriph;\r
- }\r
- else\r
- {\r
- RCC->AHBRSTR &= ~RCC_AHBPeriph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Forces or releases High Speed APB (APB2) peripheral reset.\r
- * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB2Periph_SYSCFG\r
- * @arg RCC_APB2Periph_TIM9\r
- * @arg RCC_APB2Periph_TIM10\r
- * @arg RCC_APB2Periph_TIM11\r
- * @arg RCC_APB2Periph_ADC1\r
- * @arg RCC_APB2Periph_SPI1\r
- * @arg RCC_APB2Periph_USART1 \r
- * @param NewState: new state of the specified peripheral reset.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB2RSTR |= RCC_APB2Periph;\r
- }\r
- else\r
- {\r
- RCC->APB2RSTR &= ~RCC_APB2Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Forces or releases Low Speed APB (APB1) peripheral reset.\r
- * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB1Periph_TIM2\r
- * @arg RCC_APB1Periph_TIM3\r
- * @arg RCC_APB1Periph_TIM4\r
- * @arg RCC_APB1Periph_TIM6\r
- * @arg RCC_APB1Periph_TIM7\r
- * @arg RCC_APB1Periph_LCD\r
- * @arg RCC_APB1Periph_WWDG\r
- * @arg RCC_APB1Periph_SPI2\r
- * @arg RCC_APB1Periph_USART2\r
- * @arg RCC_APB1Periph_USART3\r
- * @arg RCC_APB1Periph_I2C1\r
- * @arg RCC_APB1Periph_I2C2\r
- * @arg RCC_APB1Periph_USB\r
- * @arg RCC_APB1Periph_PWR\r
- * @arg RCC_APB1Periph_DAC\r
- * @arg RCC_APB1Periph_COMP \r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB1RSTR |= RCC_APB1Periph;\r
- }\r
- else\r
- {\r
- RCC->APB1RSTR &= ~RCC_APB1Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the AHB peripheral clock during SLEEP mode.\r
- * @note - Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * - By default, all peripheral clocks are enabled during SLEEP mode. \r
- * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_AHBPeriph_GPIOA\r
- * @arg RCC_AHBPeriph_GPIOB\r
- * @arg RCC_AHBPeriph_GPIOC \r
- * @arg RCC_AHBPeriph_GPIOD\r
- * @arg RCC_AHBPeriph_GPIOE\r
- * @arg RCC_AHBPeriph_GPIOH\r
- * @arg RCC_AHBPeriph_CRC\r
- * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) \r
- * @arg RCC_AHBPeriph_SRAM \r
- * @arg RCC_AHBPeriph_DMA1\r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- RCC->AHBLPENR |= RCC_AHBPeriph;\r
- }\r
- else\r
- {\r
- RCC->AHBLPENR &= ~RCC_AHBPeriph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the APB2 peripheral clock during SLEEP mode.\r
- * @note - Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * - By default, all peripheral clocks are enabled during SLEEP mode. \r
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB2Periph_SYSCFG\r
- * @arg RCC_APB2Periph_TIM9\r
- * @arg RCC_APB2Periph_TIM10\r
- * @arg RCC_APB2Periph_TIM11\r
- * @arg RCC_APB2Periph_ADC1\r
- * @arg RCC_APB2Periph_SPI1\r
- * @arg RCC_APB2Periph_USART1 \r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB2LPENR |= RCC_APB2Periph;\r
- }\r
- else\r
- {\r
- RCC->APB2LPENR &= ~RCC_APB2Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the APB1 peripheral clock during SLEEP mode.\r
- * @note - Peripheral clock gating in SLEEP mode can be used to further reduce\r
- * power consumption.\r
- * - After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
- * - By default, all peripheral clocks are enabled during SLEEP mode. \r
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_APB1Periph_TIM2\r
- * @arg RCC_APB1Periph_TIM3\r
- * @arg RCC_APB1Periph_TIM4\r
- * @arg RCC_APB1Periph_TIM6\r
- * @arg RCC_APB1Periph_TIM7\r
- * @arg RCC_APB1Periph_LCD\r
- * @arg RCC_APB1Periph_WWDG\r
- * @arg RCC_APB1Periph_SPI2\r
- * @arg RCC_APB1Periph_USART2\r
- * @arg RCC_APB1Periph_USART3\r
- * @arg RCC_APB1Periph_I2C1\r
- * @arg RCC_APB1Periph_I2C2\r
- * @arg RCC_APB1Periph_USB\r
- * @arg RCC_APB1Periph_PWR\r
- * @arg RCC_APB1Periph_DAC\r
- * @arg RCC_APB1Periph_COMP \r
- * @param NewState: new state of the specified peripheral clock.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- RCC->APB1LPENR |= RCC_APB1Periph;\r
- }\r
- else\r
- {\r
- RCC->APB1LPENR &= ~RCC_APB1Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RCC_Group4 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts and flags management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified RCC interrupts.\r
- * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled\r
- * and if the HSE clock fails, the CSS interrupt occurs and an NMI is\r
- * automatically generated. The NMI will be executed indefinitely, and \r
- * since NMI has higher priority than any other IRQ (and main program)\r
- * the application will be stacked in the NMI ISR unless the CSS interrupt\r
- * pending bit is cleared.\r
- * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
- * @arg RCC_IT_LSERDY: LSE ready interrupt\r
- * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
- * @arg RCC_IT_HSERDY: HSE ready interrupt\r
- * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
- * @arg RCC_IT_MSIRDY: MSI ready interrupt\r
- * @param NewState: new state of the specified RCC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_IT(RCC_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */\r
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;\r
- }\r
- else\r
- {\r
- /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */\r
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified RCC flag is set or not.\r
- * @param RCC_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
- * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready \r
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
- * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
- * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset \r
- * @arg RCC_FLAG_PINRST: Pin reset\r
- * @arg RCC_FLAG_PORRST: POR/PDR reset\r
- * @arg RCC_FLAG_SFTRST: Software reset\r
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
- * @arg RCC_FLAG_LPWRRST: Low Power reset\r
- * @retval The new state of RCC_FLAG (SET or RESET).\r
- */\r
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r
-{\r
- uint32_t tmp = 0;\r
- uint32_t statusreg = 0;\r
- FlagStatus bitstatus = RESET;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_RCC_FLAG(RCC_FLAG));\r
-\r
- /* Get the RCC register index */\r
- tmp = RCC_FLAG >> 5;\r
-\r
- if (tmp == 1) /* The flag to check is in CR register */\r
- {\r
- statusreg = RCC->CR;\r
- }\r
- else /* The flag to check is in CSR register (tmp == 2) */\r
- {\r
- statusreg = RCC->CSR;\r
- }\r
-\r
- /* Get the flag position */\r
- tmp = RCC_FLAG & FLAG_MASK;\r
-\r
- if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the flag status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the RCC reset flags.\r
- * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r
- * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.\r
- * @param None\r
- * @retval None\r
- */\r
-void RCC_ClearFlag(void)\r
-{\r
- /* Set RMVF bit to clear the reset flags */\r
- RCC->CSR |= RCC_CSR_RMVF;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified RCC interrupt has occurred or not.\r
- * @param RCC_IT: specifies the RCC interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
- * @arg RCC_IT_LSERDY: LSE ready interrupt\r
- * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
- * @arg RCC_IT_HSERDY: HSE ready interrupt\r
- * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
- * @arg RCC_IT_MSIRDY: MSI ready interrupt \r
- * @arg RCC_IT_CSS: Clock Security System interrupt\r
- * @retval The new state of RCC_IT (SET or RESET).\r
- */\r
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_RCC_GET_IT(RCC_IT));\r
- \r
- /* Check the status of the specified RCC interrupt */\r
- if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the RCC_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the RCC's interrupt pending bits.\r
- * @param RCC_IT: specifies the interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
- * @arg RCC_IT_LSERDY: LSE ready interrupt\r
- * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
- * @arg RCC_IT_HSERDY: HSE ready interrupt\r
- * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
- * @arg RCC_IT_MSIRDY: MSI ready interrupt \r
- * @arg RCC_IT_CSS: Clock Security System interrupt\r
- * @retval None\r
- */\r
-void RCC_ClearITPendingBit(uint8_t RCC_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
- \r
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
- pending bits */\r
- *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff