+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_pwr.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Power Controller (PWR) peripheral: \r
- * - RTC Domain Access\r
- * - PVD configuration\r
- * - WakeUp pins configuration\r
- * - Ultra Low Power mode configuration\r
- * - Voltage Scaling configuration\r
- * - Low Power modes configuration\r
- * - Flags management\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_pwr.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup PWR \r
- * @brief PWR driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/* --------- PWR registers bit address in the alias region ---------- */\r
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r
-\r
-/* --- CR Register ---*/\r
-\r
-/* Alias word address of DBP bit */\r
-#define CR_OFFSET (PWR_OFFSET + 0x00)\r
-#define DBP_BitNumber 0x08\r
-#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))\r
-\r
-/* Alias word address of PVDE bit */\r
-#define PVDE_BitNumber 0x04\r
-#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))\r
-\r
-/* Alias word address of ULP bit */\r
-#define ULP_BitNumber 0x09\r
-#define CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))\r
-\r
-/* Alias word address of FWU bit */\r
-#define FWU_BitNumber 0x0A\r
-#define CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))\r
-\r
-/* --- CSR Register ---*/\r
-\r
-/* Alias word address of EWUP bit */\r
-#define CSR_OFFSET (PWR_OFFSET + 0x04)\r
-#define EWUP_BitNumber 0x08\r
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))\r
-\r
-/* ------------------ PWR registers bit mask ------------------------ */\r
-\r
-/* CR register bit mask */\r
-#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)\r
-#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)\r
-#define CR_VOS_MASK ((uint32_t)0xFFFFE7FF)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup PWR_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup PWR_Group1 RTC Domain Access function \r
- * @brief RTC Domain Access function \r
- *\r
-@verbatim \r
- ===============================================================================\r
- RTC Domain Access function \r
- =============================================================================== \r
-\r
- After reset, the RTC Registers (RCC CSR Register, RTC registers and RTC backup \r
- registers) are protected against possible stray write accesses.\r
- To enable access to RTC domain use the PWR_RTCAccessCmd(ENABLE) function.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the PWR peripheral registers to their default reset values.\r
- * @note Before calling this function, the VOS[1:0] bits should be configured \r
- * to "10" and the system frequency has to be configured accordingly. \r
- * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()\r
- * function. \r
- * @note ULP and FWU bits are not reset by this function. \r
- * @param None\r
- * @retval None\r
- */\r
-void PWR_DeInit(void)\r
-{\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables access to the RTC and backup registers.\r
- * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the \r
- * RTC Domain Access should be kept enabled.\r
- * @param NewState: new state of the access to the RTC and backup registers.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_RTCAccessCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Group2 PVD configuration functions\r
- * @brief PVD configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- PVD configuration functions\r
- =============================================================================== \r
-\r
- - The PVD is used to monitor the VDD power supply by comparing it to a threshold\r
- selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r
- - The PVD can use an external input analog voltage (PVD_IN) which is compared \r
- internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode \r
- when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).\r
- - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the \r
- PVD threshold. This event is internally connected to the EXTI line16\r
- and can generate an interrupt if enabled through the EXTI registers.\r
- - The PVD is stopped in Standby mode.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
- * @param PWR_PVDLevel: specifies the PVD detection level\r
- * This parameter can be one of the following values:\r
- * @arg PWR_PVDLevel_0: PVD detection level set to 1.9V\r
- * @arg PWR_PVDLevel_1: PVD detection level set to 2.1V\r
- * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V\r
- * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V\r
- * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V\r
- * @arg PWR_PVDLevel_5: PVD detection level set to 2.9V\r
- * @arg PWR_PVDLevel_6: PVD detection level set to 3.1V\r
- * @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT)\r
- * @retval None\r
- */\r
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r
- \r
- tmpreg = PWR->CR;\r
- \r
- /* Clear PLS[7:5] bits */\r
- tmpreg &= CR_PLS_MASK;\r
- \r
- /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r
- tmpreg |= PWR_PVDLevel;\r
- \r
- /* Store the new value */\r
- PWR->CR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Power Voltage Detector(PVD).\r
- * @param NewState: new state of the PVD.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_PVDCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Group3 WakeUp pins configuration functions\r
- * @brief WakeUp pins configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- WakeUp pins configuration functions\r
- =============================================================================== \r
-\r
- - WakeUp pins are used to wakeup the system from Standby mode. These pins are \r
- forced in input pull down configuration and are active on rising edges.\r
- - There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and\r
- WakeUp Pin 3 on PE.06.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the WakeUp Pin functionality.\r
- * @param PWR_WakeUpPin: specifies the WakeUpPin.\r
- * This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.\r
- * @param NewState: new state of the WakeUp Pin functionality.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));\r
- \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- tmp = CSR_EWUP_BB + PWR_WakeUpPin;\r
- \r
- *(__IO uint32_t *) (tmp) = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Group4 Ultra Low Power mode configuration functions\r
- * @brief Ultra Low Power mode configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Ultra Low Power mode configuration functions\r
- =============================================================================== \r
-\r
- - The internal voltage reference consumption is not negligible, in particular \r
- in Stop and Standby mode. To reduce power consumption, use the PWR_UltraLowPowerCmd()\r
- function (ULP bit (Ultra low power) in the PWR_CR register) to disable the \r
- internal voltage reference. However, in this case, when exiting from the \r
- Stop/Standby mode, the functions managed through the internal voltage reference \r
- are not reliable during the internal voltage reference startup time (up to 3 ms).\r
- To reduce the wakeup time, the device can exit from Stop/Standby mode without \r
- waiting for the internal voltage reference startup time. This is performed \r
- by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast\r
- wakeup) in the PWR_CR register) before entering Stop/Standby mode.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the Fast WakeUp from Ultra Low Power mode.\r
- * @param NewState: new state of the Fast WakeUp functionality.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_FastWakeUpCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Ultra Low Power mode.\r
- * @param NewState: new state of the Ultra Low Power mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_UltraLowPowerCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Group5 Voltage Scaling configuration functions\r
- * @brief Voltage Scaling configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Voltage Scaling configuration functions\r
- =============================================================================== \r
-\r
- - The dynamic voltage scaling is a power management technique which consists in \r
- increasing or decreasing the voltage used for the digital peripherals (VCORE), \r
- according to the circumstances.\r
- \r
- Depending on the device voltage range, the maximum frequency and FLASH wait\r
- state should be adapted accordingly:\r
- \r
- +------------------------------------------------------------------+ \r
- | Wait states | HCLK clock frequency (MHz) |\r
- | |------------------------------------------------| \r
- | (Latency) | voltage range | voltage range | \r
- | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |\r
- | |----------------|---------------|---------------|\r
- | | Range 3 | Range 2 | Range 1 |\r
- | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |\r
- |---------------- |----------------|---------------|---------------| \r
- | 0WS(1CPU cycle) |0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |\r
- |-----------------|----------------|---------------|---------------| \r
- | 1WS(2CPU cycle) |2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|\r
- |-----------------|----------------|---------------|---------------| \r
- | CPU Performance | Low | Medium | High |\r
- |-----__----------|----------------|---------------|---------------| \r
- |Power Performance| High | Medium | Low | \r
- +------------------------------------------------------------------+ \r
-\r
- - To modify the Product voltage range, user application has to:\r
- - Check VDD to identify which ranges are allowed (see table above)\r
- - Check the PWR_FLAG_VOSF (Voltage Scaling update ongoing) using the PWR_GetFlagStatus() \r
- function and wait until it is reset.\r
- - Configure the Voltage range using the PWR_VoltageScalingConfig() function.\r
-\r
- - When VCORE range 1 is selected and VDD drops below 2.0 V, the application must\r
- reconfigure the system:\r
- - Detect that VDD drops below 2.0 V using the PVD Level 1\r
- - Adapt the clock frequency to the voltage range that will be selected at next step\r
- - Select the required voltage range\r
- - When VCORE range 2 or range 3 is selected and VDD drops below 2.0 V, no system\r
- reconfiguration is required.\r
- \r
- - When VDD is above 2.0 V, any of the 3 voltage ranges can be selected\r
- - When the voltage range is above the targeted voltage range (e.g. from range \r
- 1 to 2):\r
- - Adapt the clock frequency to the lower voltage range that will be selected \r
- at next step.\r
- - Select the required voltage range.\r
- - When the voltage range is below the targeted voltage range (e.g. from range \r
- 3 to 1):\r
- - Select the required voltage range.\r
- - Tune the clock frequency if needed.\r
- \r
- - When VDD is below 2.0 V, only range 2 and 3 can be selected:\r
- - From range 2 to range 3\r
- - Adapt the clock frequency to voltage range 3.\r
- - Select voltage range 3.\r
- - From range 3 to range 2\r
- - Select the voltage range 2.\r
- - Tune the clock frequency if needed.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the voltage scaling range.\r
- * @note During voltage scaling configuration, the system clock is stopped \r
- * until the regulator is stabilized (VOSF = 0). This must be taken \r
- * into account during application developement, in case a critical \r
- * reaction time to interrupt is needed, and depending on peripheral \r
- * used (timer, communication,...).\r
- * \r
- * @param PWR_VoltageScaling: specifies the voltage scaling range.\r
- * This parameter can be:\r
- * @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1 (VCORE = 1.8V)\r
- * @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2 (VCORE = 1.5V)\r
- * @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3 (VCORE = 1.2V) \r
- * @retval None\r
- */\r
-void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)\r
-{\r
- uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));\r
- \r
- tmp = PWR->CR;\r
-\r
- tmp &= CR_VOS_MASK;\r
- tmp |= PWR_VoltageScaling;\r
- \r
- PWR->CR = tmp & 0xFFFFFFF3;\r
-\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Group6 Low Power modes configuration functions\r
- * @brief Low Power modes configuration functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Low Power modes configuration functions\r
- =============================================================================== \r
-\r
- The devices feature five low-power modes:\r
- - Low power run mode: regulator in low power mode, limited clock frequency, \r
- limited number of peripherals running.\r
- - Sleep mode: Cortex-M3 core stopped, peripherals kept running.\r
- - Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, \r
- limited number of peripherals running, regulator in low power mode.\r
- - Stop mode: all clocks are stopped, regulator running, regulator in low power mode\r
- - Standby mode: VCORE domain powered off\r
- \r
- Low power run mode (LP run)\r
- ===========================\r
- - Entry:\r
- - Decrease the system frequency.\r
- - The regulator is forced in low power mode using the PWR_EnterLowPowerRunMode()\r
- function.\r
- - Exit:\r
- - The regulator is forced in Main regulator mode sing the PWR_EnterLowPowerRunMode()\r
- function.\r
- - Increase the system frequency if needed.\r
-\r
- Sleep mode\r
- ===========\r
- - Entry:\r
- - The Sleep mode is entered by using the PWR_EnterSleepMode(PWR_Regulator_ON,) \r
- function with regulator ON.\r
- - Exit:\r
- - Any peripheral interrupt acknowledged by the nested vectored interrupt \r
- controller (NVIC) can wake up the device from Sleep mode.\r
-\r
- Low power sleep mode (LP sleep)\r
- ===============================\r
- - Entry:\r
- - The Flash memory must be switched off by using the FLASH_SLEEPPowerDownCmd()\r
- function.\r
- - Decrease the system frequency.\r
- - The regulator is forced in low power mode and the WFI or WFE instructions\r
- are executed using the PWR_EnterSleepMode(PWR_Regulator_LowPower,) function \r
- with regulator in LowPower.\r
- - Exit:\r
- - Any peripheral interrupt acknowledged by the nested vectored interrupt \r
- controller (NVIC) can wake up the device from Sleep LP mode.\r
-\r
- Stop mode\r
- ==========\r
- In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI,\r
- the HSI and the HSE RC oscillators are disabled. Internal SRAM and register \r
- contents are preserved.\r
- The voltage regulator can be configured either in normal or low-power mode.\r
- To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature\r
- sensor can be switched off before entering the Stop mode. They can be switched \r
- on again by software after exiting the Stop mode using the PWR_UltraLowPowerCmd()\r
- function. \r
- \r
- - Entry:\r
- - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) \r
- function with regulator in LowPower or with Regulator ON.\r
- - Exit:\r
- - Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r
- \r
- Standby mode\r
- ============\r
- The Standby mode allows to achieve the lowest power consumption. It is based \r
- on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. \r
- The VCORE domain is consequently powered off. The PLL, the MSI, the HSI \r
- oscillator and the HSE oscillator are also switched off. SRAM and register \r
- contents are lost except for the RTC registers, RTC backup registers and \r
- Standby circuitry.\r
- \r
- The voltage regulator is OFF.\r
- \r
- To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature\r
- sensor can be switched off before entering the Standby mode. They can be switched \r
- on again by software after exiting the Standby mode using the PWR_UltraLowPowerCmd()\r
- function. \r
- \r
- - Entry:\r
- - The Standby mode is entered using the PWR_EnterSTANDBYMode() function.\r
- - Exit:\r
- - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,\r
- tamper event, time-stamp event, external reset in NRST pin, IWDG reset. \r
-\r
- Auto-wakeup (AWU) from low-power mode\r
- =====================================\r
- The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC \r
- Wakeup event, a tamper event, a time-stamp event, or a comparator event, \r
- without depending on an external interrupt (Auto-wakeup mode).\r
-\r
- - RTC auto-wakeup (AWU) from the Stop mode\r
- ----------------------------------------\r
- \r
- - To wake up from the Stop mode with an RTC alarm event, it is necessary to:\r
- - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt \r
- or Event modes) using the EXTI_Init() function.\r
- - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function\r
- - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r
- and RTC_AlarmCmd() functions.\r
- - To wake up from the Stop mode with an RTC Tamper or time stamp event, it \r
- is necessary to:\r
- - Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt \r
- or Event modes) using the EXTI_Init() function.\r
- - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r
- function\r
- - Configure the RTC to detect the tamper or time stamp event using the\r
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r
- functions.\r
- - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:\r
- - Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt \r
- or Event modes) using the EXTI_Init() function.\r
- - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function\r
- - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), \r
- RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r
-\r
- - RTC auto-wakeup (AWU) from the Standby mode\r
- -------------------------------------------\r
- - To wake up from the Standby mode with an RTC alarm event, it is necessary to:\r
- - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function\r
- - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r
- and RTC_AlarmCmd() functions.\r
- - To wake up from the Standby mode with an RTC Tamper or time stamp event, it \r
- is necessary to:\r
- - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r
- function\r
- - Configure the RTC to detect the tamper or time stamp event using the\r
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r
- functions.\r
- - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:\r
- - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function\r
- - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), \r
- RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.\r
-\r
- - Comparator auto-wakeup (AWU) from the Stop mode\r
- -----------------------------------------------\r
- - To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup\r
- event, it is necessary to:\r
- - Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 \r
- to be sensitive to to the selected edges (falling, rising or falling \r
- and rising) (Interrupt or Event modes) using the EXTI_Init() function.\r
- - Configure the comparator to generate the event.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enters/Exits the Low Power Run mode.\r
- * @note Low power run mode can only be entered when VCORE is in range 2.\r
- * In addition, the dynamic voltage scaling must not be used when Low \r
- * power run mode is selected. Only Stop and Sleep modes with regulator \r
- * configured in Low power mode is allowed when Low power run mode is \r
- * selected. \r
- * @note In Low power run mode, all I/O pins keep the same state as in Run mode. \r
- * @param NewState: new state of the Low Power Run mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_EnterLowPowerRunMode(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- PWR->CR |= PWR_CR_LPSDSR;\r
- PWR->CR |= PWR_CR_LPRUN; \r
- }\r
- else\r
- {\r
- PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN); \r
- PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR); \r
- } \r
-}\r
-\r
-/**\r
- * @brief Enters Sleep mode.\r
- * @note In Sleep mode, all I/O pins keep the same state as in Run mode. \r
- * @param PWR_Regulator: specifies the regulator state in Sleep mode.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_Regulator_ON: Sleep mode with regulator ON\r
- * @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode\r
- * @note Low power sleep mode can only be entered when VCORE is in range 2.\r
- * @note When the voltage regulator operates in low power mode, an additional \r
- * startup delay is incurred when waking up from Low power sleep mode.\r
- * \r
- * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction\r
- * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction\r
- * @retval None\r
- */\r
-void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
-\r
- assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));\r
- \r
- /* Select the regulator state in Sleep mode ---------------------------------*/\r
- tmpreg = PWR->CR;\r
- \r
- /* Clear PDDS and LPDSR bits */\r
- tmpreg &= CR_DS_MASK;\r
- \r
- /* Set LPDSR bit according to PWR_Regulator value */\r
- tmpreg |= PWR_Regulator;\r
- \r
- /* Store the new value */\r
- PWR->CR = tmpreg;\r
-\r
- /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);\r
- \r
- /* Select SLEEP mode entry -------------------------------------------------*/\r
- if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)\r
- { \r
- /* Request Wait For Interrupt */\r
- __WFI();\r
- }\r
- else\r
- {\r
- /* Request Wait For Event */\r
- __WFE();\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enters STOP mode.\r
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
- * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r
- * the MSI RC oscillator is selected as system clock.\r
- * @note When the voltage regulator operates in low power mode, an additional \r
- * startup delay is incurred when waking up from Stop mode. \r
- * By keeping the internal regulator ON during Stop mode, the consumption \r
- * is higher although the startup time is reduced. \r
- * @param PWR_Regulator: specifies the regulator state in STOP mode.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_Regulator_ON: STOP mode with regulator ON\r
- * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode\r
- * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction\r
- * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction\r
- * @retval None\r
- */\r
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r
- \r
- /* Select the regulator state in STOP mode ---------------------------------*/\r
- tmpreg = PWR->CR;\r
- /* Clear PDDS and LPDSR bits */\r
- tmpreg &= CR_DS_MASK;\r
- \r
- /* Set LPDSR bit according to PWR_Regulator value */\r
- tmpreg |= PWR_Regulator;\r
- \r
- /* Store the new value */\r
- PWR->CR = tmpreg;\r
- \r
- /* Set SLEEPDEEP bit of Cortex System Control Register */\r
- SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
- \r
- /* Select STOP mode entry --------------------------------------------------*/\r
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r
- { \r
- /* Request Wait For Interrupt */\r
- __WFI();\r
- }\r
- else\r
- {\r
- /* Request Wait For Event */\r
- __WFE();\r
- }\r
- /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); \r
-}\r
-\r
-/**\r
- * @brief Enters STANDBY mode.\r
- * @note In Standby mode, all I/O pins are high impedance except for:\r
- * - Reset pad (still available) \r
- * - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, \r
- * time-stamp, RTC Alarm out, or RTC clock calibration out.\r
- * - WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled. \r
- * @param None\r
- * @retval None\r
- */\r
-void PWR_EnterSTANDBYMode(void)\r
-{\r
- /* Clear Wakeup flag */\r
- PWR->CR |= PWR_CR_CWUF;\r
- \r
- /* Select STANDBY mode */\r
- PWR->CR |= PWR_CR_PDDS;\r
- \r
- /* Set SLEEPDEEP bit of Cortex System Control Register */\r
- SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
- \r
-/* This option is used to ensure that store operations are completed */\r
-#if defined ( __CC_ARM )\r
- __force_stores();\r
-#endif\r
- /* Request Wait For Interrupt */\r
- __WFI();\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Group7 Flags management functions\r
- * @brief Flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Flags management functions\r
- =============================================================================== \r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Checks whether the specified PWR flag is set or not.\r
- * @param PWR_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event \r
- * was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), \r
- * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.\r
- * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\r
- * resumed from StandBy mode. \r
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled \r
- * by the PWR_PVDCmd() function.\r
- * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This \r
- * flag indicates the state of the internal voltage reference, VREFINT.\r
- * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for \r
- * the internal regulator to be ready after the voltage range is changed.\r
- * The VOSF flag indicates that the regulator has reached the voltage level \r
- * defined with bits VOS[1:0] of PWR_CR register.\r
- * @arg PWR_FLAG_REGLP: Regulator LP flag. This flag is set by hardware \r
- * when the MCU is in Low power run mode.\r
- * When the MCU exits from Low power run mode, this flag stays SET until \r
- * the regulator is ready in main mode. A polling on this flag is \r
- * recommended to wait for the regulator main mode. \r
- * This flag is RESET by hardware when the regulator is ready. \r
- * @retval The new state of PWR_FLAG (SET or RESET).\r
- */\r
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_PWR_GET_FLAG(PWR_FLAG));\r
- \r
- if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the flag status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the PWR's pending flags.\r
- * @param PWR_FLAG: specifies the flag to clear.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_FLAG_WU: Wake Up flag\r
- * @arg PWR_FLAG_SB: StandBy flag\r
- * @retval None\r
- */\r
-void PWR_ClearFlag(uint32_t PWR_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r
- \r
- PWR->CR |= PWR_FLAG << 2;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff