+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l1xx_dma.c\r
- * @author MCD Application Team\r
- * @version V1.0.0\r
- * @date 31-December-2010\r
- * @brief This file provides firmware functions to manage the following \r
- * functionalities of the Direct Memory Access controller (DMA): \r
- * - Initialization and Configuration\r
- * - Data Counter\r
- * - Interrupts and flags management\r
- * \r
- * @verbatim\r
- * \r
- * =================================================================== \r
- * How to use this driver\r
- * =================================================================== \r
- * 1. Enable The DMA controller clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE)\r
- * function for DMA1 or using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE)\r
- * function for DMA2.\r
- *\r
- * 2. Enable and configure the peripheral to be connected to the DMA channel\r
- * (except for internal SRAM / FLASH memories: no initialization is \r
- * necessary). \r
- * \r
- * 3. For a given Channel, program the Source and Destination addresses, \r
- * the transfer Direction, the Buffer Size, the Peripheral and Memory\r
- * Incrementation mode and Data Size, the Circular or Normal mode, \r
- * the channel transfer Priority and the Memory-to-Memory transfer \r
- * mode (if needed) using the DMA_Init() function.\r
- *\r
- * 4. Enable the NVIC and the corresponding interrupt(s) using the function \r
- * DMA_ITConfig() if you need to use DMA interrupts. \r
- *\r
- * 5. Enable the DMA channel using the DMA_Cmd() function. \r
- * \r
- * 6. Activate the needed channel Request using PPP_DMACmd() function for\r
- * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)\r
- * The function allowing this operation is provided in each PPP peripheral\r
- * driver (ie. SPI_DMACmd for SPI peripheral). \r
- *\r
- * 7. Optionally, you can configure the number of data to be transferred\r
- * when the channel is disabled (ie. after each Transfer Complete event\r
- * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().\r
- * And you can get the number of remaining data to be transferred using \r
- * the function DMA_GetCurrDataCounter() at run time (when the DMA channel is\r
- * enabled and running). \r
- * \r
- * 8. To control DMA events you can use one of the following \r
- * two methods:\r
- * a- Check on DMA channel flags using the function DMA_GetFlagStatus(). \r
- * b- Use DMA interrupts through the function DMA_ITConfig() at initialization\r
- * phase and DMA_GetITStatus() function into interrupt routines in\r
- * communication phase. \r
- * After checking on a flag you should clear it using DMA_ClearFlag()\r
- * function. And after checking on an interrupt event you should \r
- * clear it using DMA_ClearITPendingBit() function. \r
- * \r
- * @endverbatim\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- ****************************************************************************** \r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l1xx_dma.h"\r
-#include "stm32l1xx_rcc.h"\r
-\r
-/** @addtogroup STM32L1xx_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DMA \r
- * @brief DMA driver modules\r
- * @{\r
- */ \r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-/* DMA1 Channelx interrupt pending bit masks */\r
-#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
-#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
-#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
-#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
-#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
-#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))\r
-#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))\r
-\r
-/* DMA FLAG mask */\r
-#define FLAG_MASK ((uint32_t)0x10000000)\r
-\r
-/* DMA registers Masks */\r
-#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)\r
-\r
-/* Private macro -------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-\r
-/** @defgroup DMA_Private_Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup DMA_Group1 Initialization and Configuration functions\r
- * @brief Initialization and Configuration functions\r
- *\r
-@verbatim \r
- ===============================================================================\r
- Initialization and Configuration functions\r
- =============================================================================== \r
-\r
- This subsection provides functions allowing to initialize the DMA channel source\r
- and destination addresses, incrementation and data sizes, transfer direction, \r
- buffer size, circular/normal mode selection, memory-to-memory mode selection \r
- and channel priority value.\r
- \r
- The DMA_Init() function follows the DMA configuration procedures as described in\r
- reference manual (RM0038).\r
-\r
-@endverbatim\r
- * @{\r
- */\r
- \r
-/**\r
- * @brief Deinitializes the DMAy Channelx registers to their default reset\r
- * values.\r
- * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
- * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
- * @retval None\r
- */\r
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
-\r
- /* Disable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
-\r
- /* Reset DMAy Channelx control register */\r
- DMAy_Channelx->CCR = 0;\r
- \r
- /* Reset DMAy Channelx remaining bytes register */\r
- DMAy_Channelx->CNDTR = 0;\r
- \r
- /* Reset DMAy Channelx peripheral address register */\r
- DMAy_Channelx->CPAR = 0;\r
- \r
- /* Reset DMAy Channelx memory address register */\r
- DMAy_Channelx->CMAR = 0;\r
- \r
- if (DMAy_Channelx == DMA1_Channel1)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel1 */\r
- DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel2)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel2 */\r
- DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel3)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel3 */\r
- DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel4)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel4 */\r
- DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel5)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel5 */\r
- DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel6)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel6 */\r
- DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;\r
- }\r
- else\r
- {\r
- if (DMAy_Channelx == DMA1_Channel7)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel7 */\r
- DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK; \r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the DMAy Channelx according to the specified\r
- * parameters in the DMA_InitStruct.\r
- * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
- * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that\r
- * contains the configuration information for the specified DMA Channel.\r
- * @retval None\r
- */\r
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));\r
- assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));\r
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));\r
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); \r
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r
- assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));\r
-\r
-/*--------------------------- DMAy Channelx CCR Configuration -----------------*/\r
- /* Get the DMAy_Channelx CCR value */\r
- tmpreg = DMAy_Channelx->CCR;\r
- /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r
- tmpreg &= CCR_CLEAR_MASK;\r
- /* Configure DMAy Channelx: data transfer, data size, priority level and mode */\r
- /* Set DIR bit according to DMA_DIR value */\r
- /* Set CIRC bit according to DMA_Mode value */\r
- /* Set PINC bit according to DMA_PeripheralInc value */\r
- /* Set MINC bit according to DMA_MemoryInc value */\r
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r
- /* Set MSIZE bits according to DMA_MemoryDataSize value */\r
- /* Set PL bits according to DMA_Priority value */\r
- /* Set the MEM2MEM bit according to DMA_M2M value */\r
- tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |\r
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r
- DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;\r
-\r
- /* Write to DMAy Channelx CCR */\r
- DMAy_Channelx->CCR = tmpreg;\r
-\r
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
- /* Write to DMAy Channelx CNDTR */\r
- DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;\r
-\r
-/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/\r
- /* Write to DMAy Channelx CPAR */\r
- DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r
-\r
-/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/\r
- /* Write to DMAy Channelx CMAR */\r
- DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;\r
-}\r
-\r
-/**\r
- * @brief Fills each DMA_InitStruct member with its default value.\r
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
-{\r
-/*-------------- Reset DMA init structure parameters values ------------------*/\r
- /* Initialize the DMA_PeripheralBaseAddr member */\r
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r
- /* Initialize the DMA_MemoryBaseAddr member */\r
- DMA_InitStruct->DMA_MemoryBaseAddr = 0;\r
- /* Initialize the DMA_DIR member */\r
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;\r
- /* Initialize the DMA_BufferSize member */\r
- DMA_InitStruct->DMA_BufferSize = 0;\r
- /* Initialize the DMA_PeripheralInc member */\r
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
- /* Initialize the DMA_MemoryInc member */\r
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r
- /* Initialize the DMA_PeripheralDataSize member */\r
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r
- /* Initialize the DMA_MemoryDataSize member */\r
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r
- /* Initialize the DMA_Mode member */\r
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
- /* Initialize the DMA_Priority member */\r
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r
- /* Initialize the DMA_M2M member */\r
- DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified DMAy Channelx.\r
- * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
- * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
- * @param NewState: new state of the DMAy Channelx. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR |= DMA_CCR1_EN;\r
- }\r
- else\r
- {\r
- /* Disable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Group2 Data Counter functions\r
- * @brief Data Counter functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Data Counter functions\r
- =============================================================================== \r
-\r
- This subsection provides function allowing to configure and read the buffer size\r
- (number of data to be transferred). \r
-\r
- The DMA data counter can be written only when the DMA channel is disabled \r
- (ie. after transfer complete event).\r
-\r
- The following function can be used to write the Channel data counter value:\r
- - void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);\r
-\r
-@note It is advised to use this function rather than DMA_Init() in situations where\r
- only the Data buffer needs to be reloaded.\r
-\r
- The DMA data counter can be read to indicate the number of remaining transfers for\r
- the relative DMA channel. This counter is decremented at the end of each data \r
- transfer and when the transfer is complete: \r
- - If Normal mode is selected: the counter is set to 0.\r
- - If Circular mode is selected: the counter is reloaded with the initial value\r
- (configured before enabling the DMA channel)\r
- \r
- The following function can be used to read the Channel data counter value:\r
- - uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Sets the number of data units in the current DMAy Channelx transfer.\r
- * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
- * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
- * @param DataNumber: The number of data units in the current DMAy Channelx\r
- * transfer. \r
- * @note This function can only be used when the DMAy_Channelx is disabled. \r
- * @retval None.\r
- */\r
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- \r
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
- /* Write to DMAy Channelx CNDTR */\r
- DMAy_Channelx->CNDTR = DataNumber; \r
-}\r
-\r
-/**\r
- * @brief Returns the number of remaining data units in the current\r
- * DMAy Channelx transfer.\r
- * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
- * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
- * @retval The number of remaining data units in the current DMAy Channelx\r
- * transfer.\r
- */\r
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- /* Return the number of remaining data units for DMAy Channelx */\r
- return ((uint16_t)(DMAy_Channelx->CNDTR));\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Group3 Interrupts and flags management functions\r
- * @brief Interrupts and flags management functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- Interrupts and flags management functions\r
- =============================================================================== \r
-\r
- This subsection provides functions allowing to configure the DMA Interrupts \r
- sources and check or clear the flags or pending bits status.\r
- The user should identify which mode will be used in his application to manage the\r
- DMA controller events: Polling mode or Interrupt mode. \r
- \r
- Polling Mode\r
- =============\r
- Each DMA channel can be managed through 4 event Flags:\r
- (y : DMA Controller number \r
- x : DMA channel number )\r
- 1. DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred\r
- 2. DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occured\r
- 3. DMAy_FLAG_TEx : to indicate that a Transfer Error occured.\r
- 4. DMAy_FLAG_GLx : to indicate that at least one of the events described \r
- above occured. \r
-\r
-@note Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the \r
- same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).\r
-\r
- In this Mode it is advised to use the following functions:\r
- - FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
- - void DMA_ClearFlag(uint32_t DMA_FLAG);\r
-\r
- Interrupt Mode\r
- ===============\r
- Each DMA channel can be managed through 4 Interrupts:\r
-\r
- Interrupt Source\r
- ----------------\r
- 1. DMA_IT_TC: specifies the interrupt source for the Transfer Complete event. \r
- 2. DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete event.\r
- 3. DMA_IT_TE : specifies the interrupt source for the transfer errors event.\r
- 4. DMA_IT_GL : to indicate that at least one of the interrupts described \r
- above occurred. \r
-\r
-@note Clearing DMA_IT_GL interrupt results in clearing all other interrupts of the \r
- same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).\r
- \r
- In this Mode it is advised to use the following functions:\r
- - void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
- - ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
- - void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified DMAy Channelx interrupts.\r
- * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
- * x can be 1 to 7 for DMA1 to select the DMA Channel.\r
- * @param DMA_IT: specifies the DMA interrupts sources to be enabled\r
- * or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg DMA_IT_TC: Transfer complete interrupt mask\r
- * @arg DMA_IT_HT: Half transfer interrupt mask\r
- * @arg DMA_IT_TE: Transfer error interrupt mask\r
- * @param NewState: new state of the specified DMA interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DMA interrupts */\r
- DMAy_Channelx->CCR |= DMA_IT;\r
- }\r
- else\r
- {\r
- /* Disable the selected DMA interrupts */\r
- DMAy_Channelx->CCR &= ~DMA_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DMAy Channelx flag is set or not.\r
- * @param DMA_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
- * \r
- * @note\r
- * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags \r
- * relative to the same channel is set (Transfer Complete, Half-transfer \r
- * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or \r
- * DMAy_FLAG_TEx). \r
- * \r
- * @retval The new state of DMA_FLAG (SET or RESET).\r
- */\r
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DMA_GET_FLAG(DMA_FLAG));\r
-\r
- /* Calculate the used DMA */\r
- if ((DMA_FLAG & FLAG_MASK) == (uint32_t)RESET)\r
- {\r
- /* Get DMA1 ISR register value */\r
- tmpreg = DMA1->ISR ;\r
- }\r
-\r
- /* Check the status of the specified DMA flag */\r
- if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)\r
- {\r
- /* DMA_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DMA_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- \r
- /* Return the DMA_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DMAy Channelx's pending flags.\r
- * @param DMA_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination (for the same DMA) of the following values:\r
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
- * \r
- * @note\r
- * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags\r
- * relative to the same channel (Transfer Complete, Half-transfer Complete and \r
- * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). \r
- * \r
- * @retval None\r
- */\r
-void DMA_ClearFlag(uint32_t DMA_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));\r
-\r
- if ((DMA_FLAG & FLAG_MASK) == (uint32_t)RESET)\r
- {\r
- /* Clear the selected DMA flags */\r
- DMA1->IFCR = DMA_FLAG;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.\r
- * @param DMA_IT: specifies the DMA interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
- * \r
- * @note\r
- * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other \r
- * interrupts relative to the same channel is set (Transfer Complete, \r
- * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, \r
- * DMAy_IT_HTx or DMAy_IT_TEx). \r
- * \r
- * @retval The new state of DMA_IT (SET or RESET).\r
- */\r
-ITStatus DMA_GetITStatus(uint32_t DMA_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DMA_GET_IT(DMA_IT));\r
-\r
- /* Calculate the used DMA */\r
- if ((DMA_IT & FLAG_MASK) == (uint32_t)RESET)\r
- {\r
- /* Get DMA1 ISR register value */\r
- tmpreg = DMA1->ISR ;\r
- }\r
-\r
- /* Check the status of the specified DMA interrupt */\r
- if ((tmpreg & DMA_IT) != (uint32_t)RESET)\r
- {\r
- /* DMA_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DMA_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the DMA_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DMAy Channelx\92s interrupt pending bits.\r
- * @param DMA_IT: specifies the DMA interrupt pending bit to clear.\r
- * This parameter can be any combination (for the same DMA) of the following values:\r
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
- * \r
- * @note\r
- * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other \r
- * interrupts relative to the same channel (Transfer Complete, Half-transfer \r
- * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and \r
- * DMAy_IT_TEx). \r
- * \r
- * @retval None\r
- */\r
-void DMA_ClearITPendingBit(uint32_t DMA_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_CLEAR_IT(DMA_IT));\r
-\r
- /* Calculate the used DMA */\r
- if ((DMA_IT & FLAG_MASK) == (uint32_t)RESET)\r
- {\r
- /* Clear the selected DMA interrupt pending bits */\r
- DMA1->IFCR = DMA_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff