--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_spi.c\r
+ * @author MCD Application Team\r
+ * @version V3.3.0\r
+ * @date 04/16/2010\r
+ * @brief This file provides all the SPI firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_spi.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI \r
+ * @brief SPI driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup SPI_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SPI_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* SPI SPE mask */\r
+#define CR1_SPE_Set ((uint16_t)0x0040)\r
+#define CR1_SPE_Reset ((uint16_t)0xFFBF)\r
+\r
+/* I2S I2SE mask */\r
+#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)\r
+#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)\r
+\r
+/* SPI CRCNext mask */\r
+#define CR1_CRCNext_Set ((uint16_t)0x1000)\r
+\r
+/* SPI CRCEN mask */\r
+#define CR1_CRCEN_Set ((uint16_t)0x2000)\r
+#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)\r
+\r
+/* SPI SSOE mask */\r
+#define CR2_SSOE_Set ((uint16_t)0x0004)\r
+#define CR2_SSOE_Reset ((uint16_t)0xFFFB)\r
+\r
+/* SPI registers Masks */\r
+#define CR1_CLEAR_Mask ((uint16_t)0x3040)\r
+#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)\r
+\r
+/* SPI or I2S mode selection masks */\r
+#define SPI_Mode_Select ((uint16_t)0xF7FF)\r
+#define I2S_Mode_Select ((uint16_t)0x0800) \r
+\r
+/* I2S clock source selection masks */\r
+#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))\r
+#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))\r
+#define I2S_MUL_MASK ((uint32_t)(0x0000F000))\r
+#define I2S_DIV_MASK ((uint32_t)(0x000000F0))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SPIx peripheral registers to their default\r
+ * reset values (Affects also the I2Ss).\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+\r
+ if (SPIx == SPI1)\r
+ {\r
+ /* Enable SPI1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
+ /* Release SPI1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
+ }\r
+ else if (SPIx == SPI2)\r
+ {\r
+ /* Enable SPI2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
+ /* Release SPI2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if (SPIx == SPI3)\r
+ {\r
+ /* Enable SPI3 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);\r
+ /* Release SPI3 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SPIx peripheral according to the specified \r
+ * parameters in the SPI_InitStruct.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
+ * contains the configuration information for the specified SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ \r
+ /* check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx)); \r
+ \r
+ /* Check the SPI parameters */\r
+ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r
+ assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
+ assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
+ assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
+\r
+/*---------------------------- SPIx CR1 Configuration ------------------------*/\r
+ /* Get the SPIx CR1 value */\r
+ tmpreg = SPIx->CR1;\r
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r
+ tmpreg &= CR1_CLEAR_Mask;\r
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
+ master/salve mode, CPOL and CPHA */\r
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r
+ /* Set LSBFirst bit according to SPI_FirstBit value */\r
+ /* Set BR bits according to SPI_BaudRatePrescaler value */\r
+ /* Set CPOL bit according to SPI_CPOL value */\r
+ /* Set CPHA bit according to SPI_CPHA value */\r
+ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r
+ SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | \r
+ SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | \r
+ SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r
+ /* Write to SPIx CR1 */\r
+ SPIx->CR1 = tmpreg;\r
+ \r
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */\r
+ SPIx->I2SCFGR &= SPI_Mode_Select; \r
+\r
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
+ /* Write to SPIx CRCPOLY */\r
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SPIx peripheral according to the specified \r
+ * parameters in the I2S_InitStruct.\r
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral\r
+ * (configured in I2S mode).\r
+ * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that\r
+ * contains the configuration information for the specified SPI peripheral\r
+ * configured in I2S mode.\r
+ * @note\r
+ * The function calculates the optimal prescaler needed to obtain the most \r
+ * accurate audio frequency (depending on the I2S clock source, the PLL values \r
+ * and the product configuration). But in case the prescaler value is greater \r
+ * than 511, the default value (0x02) will be configured instead. * \r
+ * @retval None\r
+ */\r
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r
+ uint32_t tmp = 0;\r
+ RCC_ClocksTypeDef RCC_Clocks;\r
+ uint32_t sourceclock = 0;\r
+ \r
+ /* Check the I2S parameters */\r
+ assert_param(IS_SPI_23_PERIPH(SPIx));\r
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));\r
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));\r
+ assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));\r
+ assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));\r
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));\r
+ assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); \r
+\r
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r
+ SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; \r
+ SPIx->I2SPR = 0x0002;\r
+ \r
+ /* Get the I2SCFGR register value */\r
+ tmpreg = SPIx->I2SCFGR;\r
+ \r
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r
+ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)\r
+ {\r
+ i2sodd = (uint16_t)0;\r
+ i2sdiv = (uint16_t)2; \r
+ }\r
+ /* If the requested audio frequency is not the default, compute the prescaler */\r
+ else\r
+ {\r
+ /* Check the frame length (For the Prescaler computing) */\r
+ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)\r
+ {\r
+ /* Packet length is 16 bits */\r
+ packetlength = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Packet length is 32 bits */\r
+ packetlength = 2;\r
+ }\r
+\r
+ /* Get the I2S clock source mask depending on the peripheral number */\r
+ if(((uint32_t)SPIx) == SPI2_BASE)\r
+ {\r
+ /* The mask is relative to I2S2 */\r
+ tmp = I2S2_CLOCK_SRC;\r
+ }\r
+ else \r
+ {\r
+ /* The mask is relative to I2S3 */ \r
+ tmp = I2S3_CLOCK_SRC;\r
+ }\r
+\r
+ /* Check the I2S clock source configuration depending on the Device:\r
+ Only Connectivity line devices have the PLL3 VCO clock */\r
+#ifdef STM32F10X_CL\r
+ if((RCC->CFGR2 & tmp) != 0)\r
+ {\r
+ /* Get the configuration bits of RCC PLL3 multiplier */\r
+ tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);\r
+\r
+ /* Get the value of the PLL3 multiplier */ \r
+ if((tmp > 5) && (tmp < 15))\r
+ {\r
+ /* Multplier is between 8 and 14 (value 15 is forbidden) */\r
+ tmp += 2;\r
+ }\r
+ else\r
+ {\r
+ if (tmp == 15)\r
+ {\r
+ /* Multiplier is 20 */\r
+ tmp = 20;\r
+ }\r
+ } \r
+ /* Get the PREDIV2 value */\r
+ sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);\r
+ \r
+ /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */\r
+ sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); \r
+ }\r
+ else\r
+ {\r
+ /* I2S Clock source is System clock: Get System Clock frequency */\r
+ RCC_GetClocksFreq(&RCC_Clocks); \r
+ \r
+ /* Get the source clock value: based on System Clock value */\r
+ sourceclock = RCC_Clocks.SYSCLK_Frequency;\r
+ } \r
+#else /* STM32F10X_HD */\r
+ /* I2S Clock source is System clock: Get System Clock frequency */\r
+ RCC_GetClocksFreq(&RCC_Clocks); \r
+ \r
+ /* Get the source clock value: based on System Clock value */\r
+ sourceclock = RCC_Clocks.SYSCLK_Frequency; \r
+#endif /* STM32F10X_CL */ \r
+\r
+ /* Compute the Real divider depending on the MCLK output state with a flaoting point */\r
+ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)\r
+ {\r
+ /* MCLK output is enabled */\r
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
+ }\r
+ else\r
+ {\r
+ /* MCLK output is disabled */\r
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
+ }\r
+ \r
+ /* Remove the flaoting point */\r
+ tmp = tmp / 10; \r
+ \r
+ /* Check the parity of the divider */\r
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);\r
+ \r
+ /* Compute the i2sdiv prescaler */\r
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);\r
+ \r
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r
+ i2sodd = (uint16_t) (i2sodd << 8);\r
+ }\r
+ \r
+ /* Test if the divider is 1 or 0 or greater than 0xFF */\r
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))\r
+ {\r
+ /* Set the default values */\r
+ i2sdiv = 2;\r
+ i2sodd = 0;\r
+ }\r
+\r
+ /* Write to SPIx I2SPR register the computed value */\r
+ SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); \r
+ \r
+ /* Configure the I2S with the SPI_InitStruct values */\r
+ tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \\r
+ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \\r
+ (uint16_t)I2S_InitStruct->I2S_CPOL))));\r
+ \r
+ /* Write to SPIx I2SCFGR */ \r
+ SPIx->I2SCFGR = tmpreg; \r
+}\r
+\r
+/**\r
+ * @brief Fills each SPI_InitStruct member with its default value.\r
+ * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+/*--------------- Reset SPI init structure parameters values -----------------*/\r
+ /* Initialize the SPI_Direction member */\r
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+ /* initialize the SPI_Mode member */\r
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
+ /* initialize the SPI_DataSize member */\r
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
+ /* Initialize the SPI_CPOL member */\r
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
+ /* Initialize the SPI_CPHA member */\r
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
+ /* Initialize the SPI_NSS member */\r
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
+ /* Initialize the SPI_BaudRatePrescaler member */\r
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+ /* Initialize the SPI_FirstBit member */\r
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
+ /* Initialize the SPI_CRCPolynomial member */\r
+ SPI_InitStruct->SPI_CRCPolynomial = 7;\r
+}\r
+\r
+/**\r
+ * @brief Fills each I2S_InitStruct member with its default value.\r
+ * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)\r
+{\r
+/*--------------- Reset I2S init structure parameters values -----------------*/\r
+ /* Initialize the I2S_Mode member */\r
+ I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;\r
+ \r
+ /* Initialize the I2S_Standard member */\r
+ I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;\r
+ \r
+ /* Initialize the I2S_DataFormat member */\r
+ I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;\r
+ \r
+ /* Initialize the I2S_MCLKOutput member */\r
+ I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;\r
+ \r
+ /* Initialize the I2S_AudioFreq member */\r
+ I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;\r
+ \r
+ /* Initialize the I2S_CPOL member */\r
+ I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI peripheral.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral */\r
+ SPIx->CR1 |= CR1_SPE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral */\r
+ SPIx->CR1 &= CR1_SPE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).\r
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_23_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral (in I2S mode) */\r
+ SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral (in I2S mode) */\r
+ SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI/I2S interrupts.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask\r
+ * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask\r
+ * @arg SPI_I2S_IT_ERR: Error interrupt mask\r
+ * @param NewState: new state of the specified SPI/I2S interrupt.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)\r
+{\r
+ uint16_t itpos = 0, itmask = 0 ;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI/I2S IT index */\r
+ itpos = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = (uint16_t)1 << (uint16_t)itpos;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI/I2S interrupt */\r
+ SPIx->CR2 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI/I2S interrupt */\r
+ SPIx->CR2 &= (uint16_t)~itmask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request\r
+ * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request\r
+ * @param NewState: new state of the selected SPI/I2S DMA transfer request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI/I2S DMA requests */\r
+ SPIx->CR2 |= SPI_I2S_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI/I2S DMA requests */\r
+ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param Data : Data to be transmitted.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Write in the DR register the data to be sent */\r
+ SPIx->DR = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. \r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @retval The value of the received data.\r
+ */\r
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the data in the DR register */\r
+ return SPIx->DR;\r
+}\r
+\r
+/**\r
+ * @brief Configures internally by software the NSS pin for the selected SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally\r
+ * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally\r
+ * @retval None\r
+ */\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
+ {\r
+ /* Set NSS pin internally by software */\r
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset NSS pin internally by software */\r
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SS output for the selected SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx SS output. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI SS output */\r
+ SPIx->CR2 |= CR2_SSOE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI SS output */\r
+ SPIx->CR2 &= CR2_SSOE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the data size for the selected SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_DataSize: specifies the SPI data size.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_DataSize_16b: Set data frame format to 16bit\r
+ * @arg SPI_DataSize_8b: Set data frame format to 8bit\r
+ * @retval None\r
+ */\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DATASIZE(SPI_DataSize));\r
+ /* Clear DFF bit */\r
+ SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;\r
+ /* Set new DFF bit value */\r
+ SPIx->CR1 |= SPI_DataSize;\r
+}\r
+\r
+/**\r
+ * @brief Transmit the SPIx CRC value.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Enable the selected SPI CRC transmission */\r
+ SPIx->CR1 |= CR1_CRCNext_Set;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CRC value calculation of the transfered bytes.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx CRC value calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI CRC calculation */\r
+ SPIx->CR1 |= CR1_CRCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI CRC calculation */\r
+ SPIx->CR1 &= CR1_CRCEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_CRC: specifies the CRC register to be read.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_CRC_Tx: Selects Tx CRC register\r
+ * @arg SPI_CRC_Rx: Selects Rx CRC register\r
+ * @retval The selected CRC register value..\r
+ */\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)\r
+{\r
+ uint16_t crcreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_CRC(SPI_CRC));\r
+ if (SPI_CRC != SPI_CRC_Rx)\r
+ {\r
+ /* Get the Tx CRC register */\r
+ crcreg = SPIx->TXCRCR;\r
+ }\r
+ else\r
+ {\r
+ /* Get the Rx CRC register */\r
+ crcreg = SPIx->RXCRCR;\r
+ }\r
+ /* Return the selected CRC register */\r
+ return crcreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the CRC Polynomial register value for the specified SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @retval The CRC Polynomial register value.\r
+ */\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the CRC polynomial register */\r
+ return SPIx->CRCPR;\r
+}\r
+\r
+/**\r
+ * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_Direction_Tx: Selects Tx transmission direction\r
+ * @arg SPI_Direction_Rx: Selects Rx receive direction\r
+ * @retval None\r
+ */\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DIRECTION(SPI_Direction));\r
+ if (SPI_Direction == SPI_Direction_Tx)\r
+ {\r
+ /* Set the Tx only mode */\r
+ SPIx->CR1 |= SPI_Direction_Tx;\r
+ }\r
+ else\r
+ {\r
+ /* Set the Rx only mode */\r
+ SPIx->CR1 &= SPI_Direction_Rx;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI/I2S flag is set or not.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.\r
+ * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.\r
+ * @arg SPI_I2S_FLAG_BSY: Busy flag.\r
+ * @arg SPI_I2S_FLAG_OVR: Overrun flag.\r
+ * @arg SPI_FLAG_MODF: Mode Fault flag.\r
+ * @arg SPI_FLAG_CRCERR: CRC Error flag.\r
+ * @arg I2S_FLAG_UDR: Underrun Error flag.\r
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag.\r
+ * @retval The new state of SPI_I2S_FLAG (SET or RESET).\r
+ */\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));\r
+ /* Check the status of the specified SPI/I2S flag */\r
+ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)\r
+ {\r
+ /* SPI_I2S_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * @param SPI_I2S_FLAG: specifies the SPI flag to clear. \r
+ * This function clears only CRCERR flag.\r
+ * @note\r
+ * - OVR (OverRun error) flag is cleared by software sequence: a read \r
+ * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).\r
+ * - UDR (UnderRun error) flag is cleared by a read operation to \r
+ * SPI_SR register (SPI_I2S_GetFlagStatus()).\r
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a \r
+ * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));\r
+ \r
+ /* Clear the selected SPI CRC Error (CRCERR) flag */\r
+ SPIx->SR = (uint16_t)~SPI_I2S_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.\r
+ * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.\r
+ * @arg SPI_I2S_IT_OVR: Overrun interrupt.\r
+ * @arg SPI_IT_MODF: Mode Fault interrupt.\r
+ * @arg SPI_IT_CRCERR: CRC Error interrupt.\r
+ * @arg I2S_IT_UDR: Underrun Error interrupt.\r
+ * @retval The new state of SPI_I2S_IT (SET or RESET).\r
+ */\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI/I2S IT index */\r
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
+\r
+ /* Get the SPI/I2S IT mask */\r
+ itmask = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = 0x01 << itmask;\r
+\r
+ /* Get the SPI_I2S_IT enable bit status */\r
+ enablestatus = (SPIx->CR2 & itmask) ;\r
+\r
+ /* Check the status of the specified SPI/I2S interrupt */\r
+ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)\r
+ {\r
+ /* SPI_I2S_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.\r
+ * This function clears only CRCERR intetrrupt pending bit. \r
+ * @note\r
+ * - OVR (OverRun Error) interrupt pending bit is cleared by software \r
+ * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) \r
+ * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
+ * - UDR (UnderRun Error) interrupt pending bit is cleared by a read \r
+ * operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r
+ * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) \r
+ * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable \r
+ * the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
+{\r
+ uint16_t itpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI IT index */\r
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
+\r
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */\r
+ SPIx->SR = (uint16_t)~itpos;\r
+}\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff