--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_rcc.c\r
+ * @author MCD Application Team\r
+ * @version V3.3.0\r
+ * @date 04/16/2010\r
+ * @brief This file provides all the RCC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC \r
+ * @brief RCC driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup RCC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of HSION bit */\r
+#define CR_OFFSET (RCC_OFFSET + 0x00)\r
+#define HSION_BitNumber 0x00\r
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
+\r
+/* Alias word address of PLLON bit */\r
+#define PLLON_BitNumber 0x18\r
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
+\r
+#ifdef STM32F10X_CL\r
+ /* Alias word address of PLL2ON bit */\r
+ #define PLL2ON_BitNumber 0x1A\r
+ #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))\r
+\r
+ /* Alias word address of PLL3ON bit */\r
+ #define PLL3ON_BitNumber 0x1C\r
+ #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))\r
+#endif /* STM32F10X_CL */ \r
+\r
+/* Alias word address of CSSON bit */\r
+#define CSSON_BitNumber 0x13\r
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
+\r
+/* --- CFGR Register ---*/\r
+\r
+/* Alias word address of USBPRE bit */\r
+#define CFGR_OFFSET (RCC_OFFSET + 0x04)\r
+\r
+#ifndef STM32F10X_CL\r
+ #define USBPRE_BitNumber 0x16\r
+ #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))\r
+#else\r
+ #define OTGFSPRE_BitNumber 0x16\r
+ #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))\r
+#endif /* STM32F10X_CL */ \r
+\r
+/* --- BDCR Register ---*/\r
+\r
+/* Alias word address of RTCEN bit */\r
+#define BDCR_OFFSET (RCC_OFFSET + 0x20)\r
+#define RTCEN_BitNumber 0x0F\r
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
+\r
+/* Alias word address of BDRST bit */\r
+#define BDRST_BitNumber 0x10\r
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of LSION bit */\r
+#define CSR_OFFSET (RCC_OFFSET + 0x24)\r
+#define LSION_BitNumber 0x00\r
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
+\r
+#ifdef STM32F10X_CL\r
+/* --- CFGR2 Register ---*/\r
+\r
+ /* Alias word address of I2S2SRC bit */\r
+ #define CFGR2_OFFSET (RCC_OFFSET + 0x2C)\r
+ #define I2S2SRC_BitNumber 0x11\r
+ #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))\r
+\r
+ /* Alias word address of I2S3SRC bit */\r
+ #define I2S3SRC_BitNumber 0x12\r
+ #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))\r
+#endif /* STM32F10X_CL */\r
+\r
+/* ---------------------- RCC registers bit mask ------------------------ */\r
+\r
+/* CR register bit mask */\r
+#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)\r
+#define CR_HSEBYP_Set ((uint32_t)0x00040000)\r
+#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)\r
+#define CR_HSEON_Set ((uint32_t)0x00010000)\r
+#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)\r
+\r
+/* CFGR register bit mask */\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) \r
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)\r
+#else\r
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)\r
+#endif /* STM32F10X_CL */ \r
+\r
+#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)\r
+#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)\r
+#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)\r
+#define CFGR_SWS_Mask ((uint32_t)0x0000000C)\r
+#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)\r
+#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)\r
+#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)\r
+#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)\r
+#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)\r
+#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)\r
+#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)\r
+#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)\r
+#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)\r
+\r
+/* CSR register bit mask */\r
+#define CSR_RMVF_Set ((uint32_t)0x01000000)\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) \r
+/* CFGR2 register bit mask */\r
+ #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)\r
+ #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)\r
+#endif\r
+#ifdef STM32F10X_CL\r
+ #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)\r
+ #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)\r
+ #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)\r
+#endif /* STM32F10X_CL */ \r
+\r
+/* RCC Flag Mask */\r
+#define FLAG_Mask ((uint8_t)0x1F)\r
+\r
+#ifndef HSI_Value\r
+/* Typical Value of the HSI in Hz */\r
+ #define HSI_Value ((uint32_t)8000000)\r
+#endif /* HSI_Value */\r
+\r
+/* CIR register byte 2 (Bits[15:8]) base address */\r
+#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)\r
+\r
+/* CIR register byte 3 (Bits[23:16]) base address */\r
+#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)\r
+\r
+/* CFGR register byte 4 (Bits[31:24]) base address */\r
+#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)\r
+\r
+/* BDCR register base address */\r
+#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)\r
+\r
+#ifndef HSEStartUp_TimeOut\r
+/* Time out for HSE start up */\r
+ #define HSEStartUp_TimeOut ((uint16_t)0x0500)\r
+#endif /* HSEStartUp_TimeOut */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_Private_Macros\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_Private_Variables\r
+ * @{\r
+ */ \r
+\r
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the RCC clock configuration to the default reset state.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_DeInit(void)\r
+{\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
+#ifndef STM32F10X_CL\r
+ RCC->CFGR &= (uint32_t)0xF8FF0000;\r
+#else\r
+ RCC->CFGR &= (uint32_t)0xF0FF0000;\r
+#endif /* STM32F10X_CL */ \r
+ \r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
+\r
+#ifdef STM32F10X_CL\r
+ /* Reset PLL2ON and PLL3ON bits */\r
+ RCC->CR &= (uint32_t)0xEBFFFFFF;\r
+\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x00FF0000;\r
+\r
+ /* Reset CFGR2 register */\r
+ RCC->CFGR2 = 0x00000000;\r
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) \r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x009F0000;\r
+\r
+ /* Reset CFGR2 register */\r
+ RCC->CFGR2 = 0x00000000; \r
+#else\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x009F0000;\r
+#endif /* STM32F10X_CL */\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the External High Speed oscillator (HSE).\r
+ * @note HSE can not be stopped if it is used directly or through the PLL as system clock.\r
+ * @param RCC_HSE: specifies the new state of the HSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HSE_OFF: HSE oscillator OFF\r
+ * @arg RCC_HSE_ON: HSE oscillator ON\r
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_HSEConfig(uint32_t RCC_HSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_HSE));\r
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
+ /* Reset HSEON bit */\r
+ RCC->CR &= CR_HSEON_Reset;\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= CR_HSEBYP_Reset;\r
+ /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */\r
+ switch(RCC_HSE)\r
+ {\r
+ case RCC_HSE_ON:\r
+ /* Set HSEON bit */\r
+ RCC->CR |= CR_HSEON_Set;\r
+ break;\r
+ \r
+ case RCC_HSE_Bypass:\r
+ /* Set HSEBYP and HSEON bits */\r
+ RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Waits for HSE start-up.\r
+ * @param None\r
+ * @retval An ErrorStatus enumuration value:\r
+ * - SUCCESS: HSE oscillator is stable and ready to use\r
+ * - ERROR: HSE oscillator not yet ready\r
+ */\r
+ErrorStatus RCC_WaitForHSEStartUp(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0;\r
+ ErrorStatus status = ERROR;\r
+ FlagStatus HSEStatus = RESET;\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
+ StartUpCounter++; \r
+ } while((StartUpCounter != HSEStartUp_TimeOut) && (HSEStatus == RESET));\r
+ \r
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ } \r
+ return (status);\r
+}\r
+\r
+/**\r
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
+ * @param HSICalibrationValue: specifies the calibration trimming value.\r
+ * This parameter must be a number between 0 and 0x1F.\r
+ * @retval None\r
+ */\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));\r
+ tmpreg = RCC->CR;\r
+ /* Clear HSITRIM[4:0] bits */\r
+ tmpreg &= CR_HSITRIM_Mask;\r
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
+ tmpreg |= (uint32_t)HSICalibrationValue << 3;\r
+ /* Store the new value */\r
+ RCC->CR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).\r
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.\r
+ * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_HSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the PLL clock source and multiplication factor.\r
+ * @note This function must be used only when the PLL is disabled.\r
+ * @param RCC_PLLSource: specifies the PLL entry clock source.\r
+ * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, \r
+ * this parameter can be one of the following values:\r
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry\r
+ * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry\r
+ * For @b other_STM32_devices, this parameter can be one of the following values:\r
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry\r
+ * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry \r
+ * @param RCC_PLLMul: specifies the PLL multiplication factor.\r
+ * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}\r
+ * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] \r
+ * @retval None\r
+ */\r
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
+\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */\r
+ tmpreg &= CFGR_PLL_Mask;\r
+ /* Set the PLL configuration bits */\r
+ tmpreg |= RCC_PLLSource | RCC_PLLMul;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PLL.\r
+ * @note The PLL can not be disabled if it is used as system clock.\r
+ * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLLCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r
+}\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL)\r
+/**\r
+ * @brief Configures the PREDIV1 division factor.\r
+ * @note \r
+ * - This function must be used only when the PLL is disabled.\r
+ * - This function applies only to STM32 Connectivity line and Value line \r
+ * devices.\r
+ * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock\r
+ * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock\r
+ * @note \r
+ * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE \r
+ * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.\r
+ * This parameter can be RCC_PREDIV1_Divx where x:[1,16]\r
+ * @retval None\r
+ */\r
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));\r
+ assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));\r
+\r
+ tmpreg = RCC->CFGR2;\r
+ /* Clear PREDIV1[3:0] and PREDIV1SRC bits */\r
+ tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);\r
+ /* Set the PREDIV1 clock source and division factor */\r
+ tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;\r
+ /* Store the new value */\r
+ RCC->CFGR2 = tmpreg;\r
+}\r
+#endif\r
+\r
+#ifdef STM32F10X_CL\r
+/**\r
+ * @brief Configures the PREDIV2 division factor.\r
+ * @note \r
+ * - This function must be used only when both PLL2 and PLL3 are disabled.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.\r
+ * This parameter can be RCC_PREDIV2_Divx where x:[1,16]\r
+ * @retval None\r
+ */\r
+void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));\r
+\r
+ tmpreg = RCC->CFGR2;\r
+ /* Clear PREDIV2[3:0] bits */\r
+ tmpreg &= ~CFGR2_PREDIV2;\r
+ /* Set the PREDIV2 division factor */\r
+ tmpreg |= RCC_PREDIV2_Div;\r
+ /* Store the new value */\r
+ RCC->CFGR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the PLL2 multiplication factor.\r
+ * @note\r
+ * - This function must be used only when the PLL2 is disabled.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor.\r
+ * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}\r
+ * @retval None\r
+ */\r
+void RCC_PLL2Config(uint32_t RCC_PLL2Mul)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));\r
+\r
+ tmpreg = RCC->CFGR2;\r
+ /* Clear PLL2Mul[3:0] bits */\r
+ tmpreg &= ~CFGR2_PLL2MUL;\r
+ /* Set the PLL2 configuration bits */\r
+ tmpreg |= RCC_PLL2Mul;\r
+ /* Store the new value */\r
+ RCC->CFGR2 = tmpreg;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the PLL2.\r
+ * @note \r
+ * - The PLL2 can not be disabled if it is used indirectly as system clock\r
+ * (i.e. it is used as PLL clock entry that is used as System clock).\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLL2Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the PLL3 multiplication factor.\r
+ * @note \r
+ * - This function must be used only when the PLL3 is disabled.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor.\r
+ * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}\r
+ * @retval None\r
+ */\r
+void RCC_PLL3Config(uint32_t RCC_PLL3Mul)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));\r
+\r
+ tmpreg = RCC->CFGR2;\r
+ /* Clear PLL3Mul[3:0] bits */\r
+ tmpreg &= ~CFGR2_PLL3MUL;\r
+ /* Set the PLL3 configuration bits */\r
+ tmpreg |= RCC_PLL3Mul;\r
+ /* Store the new value */\r
+ RCC->CFGR2 = tmpreg;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the PLL3.\r
+ * @note This function applies only to STM32 Connectivity line devices.\r
+ * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLL3Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;\r
+}\r
+#endif /* STM32F10X_CL */\r
+\r
+/**\r
+ * @brief Configures the system clock (SYSCLK).\r
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock\r
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock\r
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock\r
+ * @retval None\r
+ */\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear SW[1:0] bits */\r
+ tmpreg &= CFGR_SW_Mask;\r
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
+ tmpreg |= RCC_SYSCLKSource;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the clock source used as system clock.\r
+ * @param None\r
+ * @retval The clock source used as system clock. The returned value can\r
+ * be one of the following:\r
+ * - 0x00: HSI used as system clock\r
+ * - 0x04: HSE used as system clock\r
+ * - 0x08: PLL used as system clock\r
+ */\r
+uint8_t RCC_GetSYSCLKSource(void)\r
+{\r
+ return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));\r
+}\r
+\r
+/**\r
+ * @brief Configures the AHB clock (HCLK).\r
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
+ * the system clock (SYSCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
+ * @retval None\r
+ */\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear HPRE[3:0] bits */\r
+ tmpreg &= CFGR_HPRE_Reset_Mask;\r
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
+ tmpreg |= RCC_SYSCLK;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Low Speed APB clock (PCLK1).\r
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear PPRE1[2:0] bits */\r
+ tmpreg &= CFGR_PPRE1_Reset_Mask;\r
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the High Speed APB clock (PCLK2).\r
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear PPRE2[2:0] bits */\r
+ tmpreg &= CFGR_PPRE2_Reset_Mask;\r
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK << 3;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified RCC interrupts.\r
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination\r
+ * of the following values \r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt\r
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be any combination of the \r
+ * following values \r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * \r
+ * @param NewState: new state of the specified RCC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_IT(RCC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;\r
+ }\r
+}\r
+\r
+#ifndef STM32F10X_CL\r
+/**\r
+ * @brief Configures the USB clock (USBCLK).\r
+ * @param RCC_USBCLKSource: specifies the USB clock source. This clock is \r
+ * derived from the PLL output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB \r
+ * clock source\r
+ * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source\r
+ * @retval None\r
+ */\r
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));\r
+\r
+ *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;\r
+}\r
+#else\r
+/**\r
+ * @brief Configures the USB OTG FS clock (OTGFSCLK).\r
+ * This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.\r
+ * This clock is derived from the PLL output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source\r
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source\r
+ * @retval None\r
+ */\r
+void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));\r
+\r
+ *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;\r
+}\r
+#endif /* STM32F10X_CL */ \r
+\r
+/**\r
+ * @brief Configures the ADC clock (ADCCLK).\r
+ * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from \r
+ * the APB2 clock (PCLK2).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2\r
+ * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4\r
+ * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6\r
+ * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8\r
+ * @retval None\r
+ */\r
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_ADCCLK(RCC_PCLK2));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear ADCPRE[1:0] bits */\r
+ tmpreg &= CFGR_ADCPRE_Reset_Mask;\r
+ /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */\r
+ tmpreg |= RCC_PCLK2;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+#ifdef STM32F10X_CL\r
+/**\r
+ * @brief Configures the I2S2 clock source(I2S2CLK).\r
+ * @note\r
+ * - This function must be called before enabling I2S2 APB clock.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_I2S2CLKSource: specifies the I2S2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry\r
+ * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry\r
+ * @retval None\r
+ */\r
+void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));\r
+\r
+ *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;\r
+}\r
+\r
+/**\r
+ * @brief Configures the I2S3 clock source(I2S2CLK).\r
+ * @note\r
+ * - This function must be called before enabling I2S3 APB clock.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_I2S3CLKSource: specifies the I2S3 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry\r
+ * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry\r
+ * @retval None\r
+ */\r
+void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));\r
+\r
+ *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;\r
+}\r
+#endif /* STM32F10X_CL */\r
+\r
+/**\r
+ * @brief Configures the External Low Speed oscillator (LSE).\r
+ * @param RCC_LSE: specifies the new state of the LSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSE_OFF: LSE oscillator OFF\r
+ * @arg RCC_LSE_ON: LSE oscillator ON\r
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_LSEConfig(uint8_t RCC_LSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_LSE));\r
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
+ /* Reset LSEON bit */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;\r
+ /* Reset LSEBYP bit */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;\r
+ /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */\r
+ switch(RCC_LSE)\r
+ {\r
+ case RCC_LSE_ON:\r
+ /* Set LSEON bit */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;\r
+ break;\r
+ \r
+ case RCC_LSE_Bypass:\r
+ /* Set LSEBYP and LSEON bits */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;\r
+ break; \r
+ \r
+ default:\r
+ break; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).\r
+ * @note LSI can not be disabled if the IWDG is running.\r
+ * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_LSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the RTC clock (RTCCLK).\r
+ * @note Once the RTC clock is selected it can\92t be changed unless the Backup domain is reset.\r
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock\r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
+ /* Select the RTC clock source */\r
+ RCC->BDCR |= RCC_RTCCLKSource;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC clock.\r
+ * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.\r
+ * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Returns the frequencies of different on chip clocks.\r
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold\r
+ * the clocks frequencies.\r
+ * @retval None\r
+ */\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
+{\r
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;\r
+\r
+#ifdef STM32F10X_CL\r
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;\r
+#endif /* STM32F10X_CL */\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
+ uint32_t prediv1factor = 0;\r
+#endif\r
+ \r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & CFGR_SWS_Mask;\r
+ \r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_Value;\r
+ break;\r
+ case 0x04: /* HSE used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_Value;\r
+ break;\r
+ case 0x08: /* PLL used as system clock */\r
+\r
+ /* Get PLL clock source and multiplication factor ----------------------*/\r
+ pllmull = RCC->CFGR & CFGR_PLLMull_Mask;\r
+ pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;\r
+ \r
+#ifndef STM32F10X_CL \r
+ pllmull = ( pllmull >> 18) + 2;\r
+ \r
+ if (pllsource == 0x00)\r
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;\r
+ }\r
+ else\r
+ {\r
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
+ prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;\r
+ /* HSE oscillator clock selected as PREDIV1 clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull; \r
+ #else\r
+ /* HSE selected as PLL clock entry */\r
+ if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)\r
+ {/* HSE oscillator clock divided by 2 */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;\r
+ }\r
+ else\r
+ {\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;\r
+ }\r
+ #endif\r
+ }\r
+#else\r
+ pllmull = pllmull >> 18;\r
+ \r
+ if (pllmull != 0x0D)\r
+ {\r
+ pllmull += 2;\r
+ }\r
+ else\r
+ { /* PLL multiplication factor = PLL input clock * 6.5 */\r
+ pllmull = 13 / 2; \r
+ }\r
+ \r
+ if (pllsource == 0x00)\r
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;\r
+ }\r
+ else\r
+ {/* PREDIV1 selected as PLL clock entry */\r
+ \r
+ /* Get PREDIV1 clock source and division factor */\r
+ prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;\r
+ prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;\r
+ \r
+ if (prediv1source == 0)\r
+ { /* HSE oscillator clock selected as PREDIV1 clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull; \r
+ }\r
+ else\r
+ {/* PLL2 clock selected as PREDIV1 clock entry */\r
+ \r
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */\r
+ prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;\r
+ pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; \r
+ RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull; \r
+ }\r
+ }\r
+#endif /* STM32F10X_CL */ \r
+ break;\r
+\r
+ default:\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_Value;\r
+ break;\r
+ }\r
+\r
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;\r
+ tmp = tmp >> 4;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* HCLK clock frequency */\r
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
+ /* Get PCLK1 prescaler */\r
+ tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;\r
+ tmp = tmp >> 8;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK1 clock frequency */\r
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+ /* Get PCLK2 prescaler */\r
+ tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;\r
+ tmp = tmp >> 11;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK2 clock frequency */\r
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+ /* Get ADCCLK prescaler */\r
+ tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;\r
+ tmp = tmp >> 14;\r
+ presc = ADCPrescTable[tmp];\r
+ /* ADCCLK clock frequency */\r
+ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB peripheral clock.\r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination\r
+ * of the following values: \r
+ * @arg RCC_AHBPeriph_DMA1\r
+ * @arg RCC_AHBPeriph_DMA2\r
+ * @arg RCC_AHBPeriph_SRAM\r
+ * @arg RCC_AHBPeriph_FLITF\r
+ * @arg RCC_AHBPeriph_CRC\r
+ * @arg RCC_AHBPeriph_OTG_FS \r
+ * @arg RCC_AHBPeriph_ETH_MAC \r
+ * @arg RCC_AHBPeriph_ETH_MAC_Tx\r
+ * @arg RCC_AHBPeriph_ETH_MAC_Rx\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be any combination of the \r
+ * following values: \r
+ * @arg RCC_AHBPeriph_DMA1\r
+ * @arg RCC_AHBPeriph_DMA2\r
+ * @arg RCC_AHBPeriph_SRAM\r
+ * @arg RCC_AHBPeriph_FLITF\r
+ * @arg RCC_AHBPeriph_CRC\r
+ * @arg RCC_AHBPeriph_FSMC\r
+ * @arg RCC_AHBPeriph_SDIO\r
+ * \r
+ * @note SRAM and FLITF clock can be disabled only during sleep mode.\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBENR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBENR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,\r
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,\r
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,\r
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,\r
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,\r
+ * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,\r
+ * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2ENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2ENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,\r
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,\r
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,\r
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, \r
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,\r
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,\r
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,\r
+ * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1ENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1ENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+#ifdef STM32F10X_CL\r
+/**\r
+ * @brief Forces or releases AHB peripheral reset.\r
+ * @note This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_OTG_FS \r
+ * @arg RCC_AHBPeriph_ETH_MAC\r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBRSTR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBRSTR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+#endif /* STM32F10X_CL */ \r
+\r
+/**\r
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,\r
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,\r
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,\r
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,\r
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,\r
+ * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,\r
+ * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 \r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2RSTR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2RSTR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,\r
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,\r
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,\r
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, \r
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,\r
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,\r
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,\r
+ * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1RSTR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1RSTR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases the Backup domain reset.\r
+ * @param NewState: new state of the Backup domain reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_BackupResetCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Clock Security System.\r
+ * @param NewState: new state of the Clock Security System..\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO pin.\r
+ * @param RCC_MCO: specifies the clock source to output.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the\r
+ * following values: \r
+ * @arg RCC_MCO_NoClock: No clock selected\r
+ * @arg RCC_MCO_SYSCLK: System clock selected\r
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected\r
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected\r
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected\r
+ * @arg RCC_MCO_PLL2CLK: PLL2 clock selected \r
+ * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected \r
+ * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected \r
+ * @arg RCC_MCO_PLL3CLK: PLL3 clock selected \r
+ * \r
+ * For @b other_STM32_devices, this parameter can be one of the following values: \r
+ * @arg RCC_MCO_NoClock: No clock selected\r
+ * @arg RCC_MCO_SYSCLK: System clock selected\r
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected\r
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected\r
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_MCOConfig(uint8_t RCC_MCO)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO(RCC_MCO));\r
+\r
+ /* Perform Byte access to MCO bits to select the MCO source */\r
+ *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC flag is set or not.\r
+ * @param RCC_FLAG: specifies the flag to check.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the\r
+ * following values:\r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
+ * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready \r
+ * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready \r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+ * @arg RCC_FLAG_PINRST: Pin reset\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset\r
+ * @arg RCC_FLAG_SFTRST: Software reset\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be one of the following values: \r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+ * @arg RCC_FLAG_PINRST: Pin reset\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset\r
+ * @arg RCC_FLAG_SFTRST: Software reset\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset\r
+ * \r
+ * @retval The new state of RCC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t statusreg = 0;\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_FLAG(RCC_FLAG));\r
+\r
+ /* Get the RCC register index */\r
+ tmp = RCC_FLAG >> 5;\r
+ if (tmp == 1) /* The flag to check is in CR register */\r
+ {\r
+ statusreg = RCC->CR;\r
+ }\r
+ else if (tmp == 2) /* The flag to check is in BDCR register */\r
+ {\r
+ statusreg = RCC->BDCR;\r
+ }\r
+ else /* The flag to check is in CSR register */\r
+ {\r
+ statusreg = RCC->CSR;\r
+ }\r
+\r
+ /* Get the flag position */\r
+ tmp = RCC_FLAG & FLAG_Mask;\r
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC reset flags.\r
+ * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,\r
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_ClearFlag(void)\r
+{\r
+ /* Set RMVF bit to clear the reset flags */\r
+ RCC->CSR |= CSR_RMVF_Set;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC interrupt has occurred or not.\r
+ * @param RCC_IT: specifies the RCC interrupt source to check.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the\r
+ * following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt \r
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be one of the following values: \r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * \r
+ * @retval The new state of RCC_IT (SET or RESET).\r
+ */\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_GET_IT(RCC_IT));\r
+\r
+ /* Check the status of the specified RCC interrupt */\r
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the RCC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC\92s interrupt pending bits.\r
+ * @param RCC_IT: specifies the interrupt pending bit to clear.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination\r
+ * of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt \r
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be any combination of the\r
+ * following values: \r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval None\r
+ */\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
+\r
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
+ pending bits */\r
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff