--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_gpio.c\r
+ * @author MCD Application Team\r
+ * @version V3.3.0\r
+ * @date 04/16/2010\r
+ * @brief This file provides all the GPIO firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_gpio.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO \r
+ * @brief GPIO driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup GPIO_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ------------ RCC registers bit address in the alias region ----------------*/\r
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)\r
+\r
+/* --- EVENTCR Register -----*/\r
+\r
+/* Alias word address of EVOE bit */\r
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)\r
+#define EVOE_BitNumber ((uint8_t)0x07)\r
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))\r
+\r
+\r
+/* --- MAPR Register ---*/ \r
+/* Alias word address of MII_RMII_SEL bit */ \r
+#define MAPR_OFFSET (AFIO_OFFSET + 0x04) \r
+#define MII_RMII_SEL_BitNumber ((u8)0x17) \r
+#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))\r
+\r
+\r
+#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)\r
+#define LSB_MASK ((uint16_t)0xFFFF)\r
+#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)\r
+#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)\r
+#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)\r
+#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset values.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ if (GPIOx == GPIOA)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOB)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOC)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOD)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);\r
+ } \r
+ else if (GPIOx == GPIOE)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);\r
+ } \r
+ else if (GPIOx == GPIOF)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if (GPIOx == GPIOG)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the Alternate Functions (remap, event control\r
+ * and EXTI configuration) registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void GPIO_AFIODeInit(void)\r
+{\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the GPIOx peripheral according to the specified\r
+ * parameters in the GPIO_InitStruct.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that\r
+ * contains the configuration information for the specified GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;\r
+ uint32_t tmpreg = 0x00, pinmask = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); \r
+ \r
+/*---------------------------- GPIO Mode Configuration -----------------------*/\r
+ currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);\r
+ if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)\r
+ { \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
+ /* Output mode */\r
+ currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;\r
+ }\r
+/*---------------------------- GPIO CRL Configuration ------------------------*/\r
+ /* Configure the eight low port pins */\r
+ if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)\r
+ {\r
+ tmpreg = GPIOx->CRL;\r
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)\r
+ {\r
+ pos = ((uint32_t)0x01) << pinpos;\r
+ /* Get the port pins position */\r
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
+ if (currentpin == pos)\r
+ {\r
+ pos = pinpos << 2;\r
+ /* Clear the corresponding low control register bits */\r
+ pinmask = ((uint32_t)0x0F) << pos;\r
+ tmpreg &= ~pinmask;\r
+ /* Write the mode configuration in the corresponding bits */\r
+ tmpreg |= (currentmode << pos);\r
+ /* Reset the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)\r
+ {\r
+ GPIOx->BRR = (((uint32_t)0x01) << pinpos);\r
+ }\r
+ else\r
+ {\r
+ /* Set the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)\r
+ {\r
+ GPIOx->BSRR = (((uint32_t)0x01) << pinpos);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ GPIOx->CRL = tmpreg;\r
+ }\r
+/*---------------------------- GPIO CRH Configuration ------------------------*/\r
+ /* Configure the eight high port pins */\r
+ if (GPIO_InitStruct->GPIO_Pin > 0x00FF)\r
+ {\r
+ tmpreg = GPIOx->CRH;\r
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)\r
+ {\r
+ pos = (((uint32_t)0x01) << (pinpos + 0x08));\r
+ /* Get the port pins position */\r
+ currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);\r
+ if (currentpin == pos)\r
+ {\r
+ pos = pinpos << 2;\r
+ /* Clear the corresponding high control register bits */\r
+ pinmask = ((uint32_t)0x0F) << pos;\r
+ tmpreg &= ~pinmask;\r
+ /* Write the mode configuration in the corresponding bits */\r
+ tmpreg |= (currentmode << pos);\r
+ /* Reset the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)\r
+ {\r
+ GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));\r
+ }\r
+ /* Set the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)\r
+ {\r
+ GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));\r
+ }\r
+ }\r
+ }\r
+ GPIOx->CRH = tmpreg;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each GPIO_InitStruct member with its default value.\r
+ * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ /* Reset GPIO init structure parameters values */\r
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The input port pin value.\r
+ */\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); \r
+ \r
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO input data port.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @retval GPIO input data port value.\r
+ */\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((uint16_t)GPIOx->IDR);\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified output data port bit.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The output port pin value.\r
+ */\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); \r
+ \r
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO output data port.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @retval GPIO output data port value.\r
+ */\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((uint16_t)GPIOx->ODR);\r
+}\r
+\r
+/**\r
+ * @brief Sets the selected data port bits.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BSRR = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Clears the selected data port bits.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BRR = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Sets or clears the selected data port bit.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).\r
+ * @param BitVal: specifies the value to be written to the selected bit.\r
+ * This parameter can be one of the BitAction enum values:\r
+ * @arg Bit_RESET: to clear the port pin\r
+ * @arg Bit_SET: to set the port pin\r
+ * @retval None\r
+ */\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_BIT_ACTION(BitVal)); \r
+ \r
+ if (BitVal != Bit_RESET)\r
+ {\r
+ GPIOx->BSRR = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BRR = GPIO_Pin;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes data to the specified GPIO data port.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param PortVal: specifies the value to be written to the port output data register.\r
+ * @retval None\r
+ */\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ GPIOx->ODR = PortVal;\r
+}\r
+\r
+/**\r
+ * @brief Locks GPIO Pins configuration registers.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint32_t tmp = 0x00010000;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKK bit */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+}\r
+\r
+/**\r
+ * @brief Selects the GPIO pin used as Event output.\r
+ * @param GPIO_PortSource: selects the GPIO port to be used as source\r
+ * for Event output.\r
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).\r
+ * @param GPIO_PinSource: specifies the pin for the Event output.\r
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)\r
+{\r
+ uint32_t tmpreg = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));\r
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ \r
+ tmpreg = AFIO->EVCR;\r
+ /* Clear the PORT[6:4] and PIN[3:0] bits */\r
+ tmpreg &= EVCR_PORTPINCONFIG_MASK;\r
+ tmpreg |= (uint32_t)GPIO_PortSource << 0x04;\r
+ tmpreg |= GPIO_PinSource;\r
+ AFIO->EVCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Event Output.\r
+ * @param NewState: new state of the Event output.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void GPIO_EventOutputCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Changes the mapping of the specified pin.\r
+ * @param GPIO_Remap: selects the pin to remap.\r
+ * This parameter can be one of the following values:\r
+ * @arg GPIO_Remap_SPI1\r
+ * @arg GPIO_Remap_I2C1\r
+ * @arg GPIO_Remap_USART1\r
+ * @arg GPIO_Remap_USART2\r
+ * @arg GPIO_PartialRemap_USART3\r
+ * @arg GPIO_FullRemap_USART3\r
+ * @arg GPIO_PartialRemap_TIM1\r
+ * @arg GPIO_FullRemap_TIM1\r
+ * @arg GPIO_PartialRemap1_TIM2\r
+ * @arg GPIO_PartialRemap2_TIM2\r
+ * @arg GPIO_FullRemap_TIM2\r
+ * @arg GPIO_PartialRemap_TIM3\r
+ * @arg GPIO_FullRemap_TIM3\r
+ * @arg GPIO_Remap_TIM4\r
+ * @arg GPIO_Remap1_CAN1\r
+ * @arg GPIO_Remap2_CAN1\r
+ * @arg GPIO_Remap_PD01\r
+ * @arg GPIO_Remap_TIM5CH4_LSI\r
+ * @arg GPIO_Remap_ADC1_ETRGINJ\r
+ * @arg GPIO_Remap_ADC1_ETRGREG\r
+ * @arg GPIO_Remap_ADC2_ETRGINJ\r
+ * @arg GPIO_Remap_ADC2_ETRGREG\r
+ * @arg GPIO_Remap_ETH\r
+ * @arg GPIO_Remap_CAN2 \r
+ * @arg GPIO_Remap_SWJ_NoJTRST\r
+ * @arg GPIO_Remap_SWJ_JTAGDisable\r
+ * @arg GPIO_Remap_SWJ_Disable\r
+ * @arg GPIO_Remap_SPI3\r
+ * @arg GPIO_Remap_TIM2ITR1_PTP_SOF\r
+ * @arg GPIO_Remap_PTP_PPS\r
+ * @arg GPIO_Remap_TIM15\r
+ * @arg GPIO_Remap_TIM16\r
+ * @arg GPIO_Remap_TIM17\r
+ * @arg GPIO_Remap_CEC\r
+ * @arg GPIO_Remap_TIM1_DMA \r
+ * @arg GPIO_Remap_TIM9\r
+ * @arg GPIO_Remap_TIM10\r
+ * @arg GPIO_Remap_TIM11\r
+ * @arg GPIO_Remap_TIM13\r
+ * @arg GPIO_Remap_TIM14\r
+ * @arg GPIO_Remap_FSMC_NADV \r
+ * @note If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected \r
+ * to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. \r
+ * @param NewState: new state of the port pin remapping.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)\r
+{\r
+ uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_REMAP(GPIO_Remap));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if((GPIO_Remap & 0x80000000) == 0x80000000)\r
+ {\r
+ tmpreg = AFIO->MAPR2;\r
+ }\r
+ else\r
+ {\r
+ tmpreg = AFIO->MAPR;\r
+ }\r
+\r
+ tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;\r
+ tmp = GPIO_Remap & LSB_MASK;\r
+\r
+ if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))\r
+ {\r
+ tmpreg &= DBGAFR_SWJCFG_MASK;\r
+ AFIO->MAPR &= DBGAFR_SWJCFG_MASK;\r
+ }\r
+ else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)\r
+ {\r
+ tmp1 = ((uint32_t)0x03) << tmpmask;\r
+ tmpreg &= ~tmp1;\r
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;\r
+ }\r
+ else\r
+ {\r
+ tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));\r
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;\r
+ }\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));\r
+ }\r
+\r
+ if((GPIO_Remap & 0x80000000) == 0x80000000)\r
+ {\r
+ AFIO->MAPR2 = tmpreg;\r
+ }\r
+ else\r
+ {\r
+ AFIO->MAPR = tmpreg;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Selects the GPIO pin used as EXTI Line.\r
+ * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.\r
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).\r
+ * @param GPIO_PinSource: specifies the EXTI line to be configured.\r
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)\r
+{\r
+ uint32_t tmp = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));\r
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ \r
+ tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));\r
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;\r
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));\r
+}\r
+\r
+/**\r
+ * @brief Selects the Ethernet media interface.\r
+ * @note This function applies only to STM32 Connectivity line devices. \r
+ * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg GPIO_ETH_MediaInterface_MII: MII mode\r
+ * @arg GPIO_ETH_MediaInterface_RMII: RMII mode \r
+ * @retval None\r
+ */\r
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) \r
+{ \r
+ assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); \r
+\r
+ /* Configure MII_RMII selection bit */ \r
+ *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; \r
+}\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff