--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dma.c\r
+ * @author MCD Application Team\r
+ * @version V3.3.0\r
+ * @date 04/16/2010\r
+ * @brief This file provides all the DMA firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_dma.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA \r
+ * @brief DMA driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DMA_Private_TypesDefinitions\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* DMA ENABLE mask */\r
+#define CCR_ENABLE_Set ((uint32_t)0x00000001)\r
+#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE)\r
+\r
+/* DMA1 Channelx interrupt pending bit masks */\r
+#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F)\r
+#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0)\r
+#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00)\r
+#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000)\r
+#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000)\r
+#define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000)\r
+#define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000)\r
+\r
+/* DMA2 Channelx interrupt pending bit masks */\r
+#define DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F)\r
+#define DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0)\r
+#define DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00)\r
+#define DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000)\r
+#define DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000)\r
+\r
+/* DMA2 FLAG mask */\r
+#define FLAG_Mask ((uint32_t)0x10000000)\r
+\r
+/* DMA registers Masks */\r
+#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the DMAy Channelx registers to their default reset\r
+ * values.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= CCR_ENABLE_Reset;\r
+ /* Reset DMAy Channelx control register */\r
+ DMAy_Channelx->CCR = 0;\r
+ \r
+ /* Reset DMAy Channelx remaining bytes register */\r
+ DMAy_Channelx->CNDTR = 0;\r
+ \r
+ /* Reset DMAy Channelx peripheral address register */\r
+ DMAy_Channelx->CPAR = 0;\r
+ \r
+ /* Reset DMAy Channelx memory address register */\r
+ DMAy_Channelx->CMAR = 0;\r
+ \r
+ if (DMAy_Channelx == DMA1_Channel1)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel1 */\r
+ DMA1->IFCR |= DMA1_Channel1_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel2)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel2 */\r
+ DMA1->IFCR |= DMA1_Channel2_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel3)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel3 */\r
+ DMA1->IFCR |= DMA1_Channel3_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel4)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel4 */\r
+ DMA1->IFCR |= DMA1_Channel4_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel5)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel5 */\r
+ DMA1->IFCR |= DMA1_Channel5_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel6)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel6 */\r
+ DMA1->IFCR |= DMA1_Channel6_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel7)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel7 */\r
+ DMA1->IFCR |= DMA1_Channel7_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel1)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel1 */\r
+ DMA2->IFCR |= DMA2_Channel1_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel2)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel2 */\r
+ DMA2->IFCR |= DMA2_Channel2_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel3)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel3 */\r
+ DMA2->IFCR |= DMA2_Channel3_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel4)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel4 */\r
+ DMA2->IFCR |= DMA2_Channel4_IT_Mask;\r
+ }\r
+ else\r
+ { \r
+ if (DMAy_Channelx == DMA2_Channel5)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel5 */\r
+ DMA2->IFCR |= DMA2_Channel5_IT_Mask;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMAy Channelx according to the specified\r
+ * parameters in the DMA_InitStruct.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that\r
+ * contains the configuration information for the specified DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));\r
+ assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));\r
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));\r
+ assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); \r
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r
+ assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r
+ assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r
+ assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));\r
+\r
+/*--------------------------- DMAy Channelx CCR Configuration -----------------*/\r
+ /* Get the DMAy_Channelx CCR value */\r
+ tmpreg = DMAy_Channelx->CCR;\r
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r
+ tmpreg &= CCR_CLEAR_Mask;\r
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */\r
+ /* Set DIR bit according to DMA_DIR value */\r
+ /* Set CIRC bit according to DMA_Mode value */\r
+ /* Set PINC bit according to DMA_PeripheralInc value */\r
+ /* Set MINC bit according to DMA_MemoryInc value */\r
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */\r
+ /* Set PL bits according to DMA_Priority value */\r
+ /* Set the MEM2MEM bit according to DMA_M2M value */\r
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |\r
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;\r
+\r
+ /* Write to DMAy Channelx CCR */\r
+ DMAy_Channelx->CCR = tmpreg;\r
+\r
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
+ /* Write to DMAy Channelx CNDTR */\r
+ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;\r
+\r
+/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/\r
+ /* Write to DMAy Channelx CPAR */\r
+ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r
+\r
+/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/\r
+ /* Write to DMAy Channelx CMAR */\r
+ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DMA_InitStruct member with its default value.\r
+ * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+/*-------------- Reset DMA init structure parameters values ------------------*/\r
+ /* Initialize the DMA_PeripheralBaseAddr member */\r
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r
+ /* Initialize the DMA_MemoryBaseAddr member */\r
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;\r
+ /* Initialize the DMA_DIR member */\r
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;\r
+ /* Initialize the DMA_BufferSize member */\r
+ DMA_InitStruct->DMA_BufferSize = 0;\r
+ /* Initialize the DMA_PeripheralInc member */\r
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
+ /* Initialize the DMA_MemoryInc member */\r
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r
+ /* Initialize the DMA_PeripheralDataSize member */\r
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r
+ /* Initialize the DMA_MemoryDataSize member */\r
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r
+ /* Initialize the DMA_Mode member */\r
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
+ /* Initialize the DMA_Priority member */\r
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r
+ /* Initialize the DMA_M2M member */\r
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param NewState: new state of the DMAy Channelx. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR |= CCR_ENABLE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= CCR_ENABLE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx interrupts.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param DMA_IT: specifies the DMA interrupts sources to be enabled\r
+ * or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA_IT_HT: Half transfer interrupt mask\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask\r
+ * @param NewState: new state of the specified DMA interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR |= DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR &= ~DMA_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the number of remaining data units in the current\r
+ * DMAy Channelx transfer.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @retval The number of remaining data units in the current DMAy Channelx\r
+ * transfer.\r
+ */\r
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ /* Return the number of remaining data units for DMAy Channelx */\r
+ return ((uint16_t)(DMAy_Channelx->CNDTR));\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.\r
+ * @param DMA_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.\r
+ * @retval The new state of DMA_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_FLAG(DMA_FLAG));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)\r
+ {\r
+ /* Get DMA2 ISR register value */\r
+ tmpreg = DMA2->ISR ;\r
+ }\r
+ else\r
+ {\r
+ /* Get DMA1 ISR register value */\r
+ tmpreg = DMA1->ISR ;\r
+ }\r
+\r
+ /* Check the status of the specified DMA flag */\r
+ if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* DMA_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the DMA_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx's pending flags.\r
+ * @param DMA_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.\r
+ * @retval None\r
+ */\r
+void DMA_ClearFlag(uint32_t DMA_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));\r
+ /* Calculate the used DMA */\r
+\r
+ if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)\r
+ {\r
+ /* Clear the selected DMA flags */\r
+ DMA2->IFCR = DMA_FLAG;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the selected DMA flags */\r
+ DMA1->IFCR = DMA_FLAG;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.\r
+ * @param DMA_IT: specifies the DMA interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.\r
+ * @retval The new state of DMA_IT (SET or RESET).\r
+ */\r
+ITStatus DMA_GetITStatus(uint32_t DMA_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_IT(DMA_IT));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)\r
+ {\r
+ /* Get DMA2 ISR register value */\r
+ tmpreg = DMA2->ISR ;\r
+ }\r
+ else\r
+ {\r
+ /* Get DMA1 ISR register value */\r
+ tmpreg = DMA1->ISR ;\r
+ }\r
+\r
+ /* Check the status of the specified DMA interrupt */\r
+ if ((tmpreg & DMA_IT) != (uint32_t)RESET)\r
+ {\r
+ /* DMA_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DMA_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx\92s interrupt pending bits.\r
+ * @param DMA_IT: specifies the DMA interrupt pending bit to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.\r
+ * @retval None\r
+ */\r
+void DMA_ClearITPendingBit(uint32_t DMA_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_IT(DMA_IT));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)\r
+ {\r
+ /* Clear the selected DMA interrupt pending bits */\r
+ DMA2->IFCR = DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the selected DMA interrupt pending bits */\r
+ DMA1->IFCR = DMA_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff