--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dac.c\r
+ * @author MCD Application Team\r
+ * @version V3.3.0\r
+ * @date 04/16/2010\r
+ * @brief This file provides all the DAC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_dac.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC \r
+ * @brief DAC driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DAC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* DAC EN mask */\r
+#define CR_EN_Set ((uint32_t)0x00000001)\r
+\r
+/* DAC DMAEN mask */\r
+#define CR_DMAEN_Set ((uint32_t)0x00001000)\r
+\r
+/* CR register Mask */\r
+#define CR_CLEAR_Mask ((uint32_t)0x00000FFE)\r
+\r
+/* DAC SWTRIG mask */\r
+#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001)\r
+\r
+/* DAC Dual Channels SWTRIG masks */\r
+#define DUAL_SWTRIG_Set ((uint32_t)0x00000003)\r
+#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC)\r
+\r
+/* DHR registers offsets */\r
+#define DHR12R1_Offset ((uint32_t)0x00000008)\r
+#define DHR12R2_Offset ((uint32_t)0x00000014)\r
+#define DHR12RD_Offset ((uint32_t)0x00000020)\r
+\r
+/* DOR register offset */\r
+#define DOR_Offset ((uint32_t)0x0000002C)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DAC_DeInit(void)\r
+{\r
+ /* Enable DAC reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);\r
+ /* Release DAC from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DAC peripheral according to the specified \r
+ * parameters in the DAC_InitStruct.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that\r
+ * contains the configuration information for the specified DAC channel.\r
+ * @retval None\r
+ */\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+ /* Check the DAC parameters */\r
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));\r
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));\r
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));\r
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));\r
+/*---------------------------- DAC CR Configuration --------------------------*/\r
+ /* Get the DAC CR value */\r
+ tmpreg1 = DAC->CR;\r
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r
+ tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel);\r
+ /* Configure for the selected DAC channel: buffer output, trigger, wave genration,\r
+ mask/amplitude for wave genration */\r
+ /* Set TSELx and TENx bits according to DAC_Trigger value */\r
+ /* Set WAVEx bits according to DAC_WaveGeneration value */\r
+ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ \r
+ /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);\r
+ /* Calculate CR register value depending on DAC_Channel */\r
+ tmpreg1 |= tmpreg2 << DAC_Channel;\r
+ /* Write to DAC CR */\r
+ DAC->CR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DAC_InitStruct member with its default value.\r
+ * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+/*--------------- Reset DAC init structure parameters values -----------------*/\r
+ /* Initialize the DAC_Trigger member */\r
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;\r
+ /* Initialize the DAC_WaveGeneration member */\r
+ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;\r
+ /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;\r
+ /* Initialize the DAC_OutputBuffer member */\r
+ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the DAC channel. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel */\r
+ DAC->CR |= CR_EN_Set << DAC_Channel;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel */\r
+ DAC->CR &= ~(CR_EN_Set << DAC_Channel);\r
+ }\r
+}\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
+/**\r
+ * @brief Enables or disables the specified DAC interrupts.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. \r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
+ * @param NewState: new state of the specified DAC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */ \r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC interrupts */\r
+ DAC->CR |= (DAC_IT << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC interrupts */\r
+ DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));\r
+ }\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel DMA request.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel DMA request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel DMA request */\r
+ DAC->CR |= CR_DMAEN_Set << DAC_Channel;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel DMA request */\r
+ DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel software trigger.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel software trigger.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4);\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables simultaneously the two DAC channels software\r
+ * triggers.\r
+ * @param NewState: new state of the DAC channels software triggers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for both DAC channels */\r
+ DAC->SWTRIGR |= DUAL_SWTRIG_Set ;\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for both DAC channels */\r
+ DAC->SWTRIGR &= DUAL_SWTRIG_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel wave generation.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_Wave: Specifies the wave type to enable or disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Wave_Noise: noise wave generation\r
+ * @arg DAC_Wave_Triangle: triangle wave generation\r
+ * @param NewState: new state of the selected DAC channel wave generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_WAVE(DAC_Wave)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected wave generation for the selected DAC channel */\r
+ DAC->CR |= DAC_Wave << DAC_Channel;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected wave generation for the selected DAC channel */\r
+ DAC->CR &= ~(DAC_Wave << DAC_Channel);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel1.\r
+ * @param DAC_Align: Specifies the data alignement for DAC channel1.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
+ * @param Data : Data to be loaded in the selected data holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)\r
+{ \r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)DAC_BASE; \r
+ tmp += DHR12R1_Offset + DAC_Align;\r
+\r
+ /* Set the DAC channel1 selected data holding register */\r
+ *(__IO uint32_t *) tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel2.\r
+ * @param DAC_Align: Specifies the data alignement for DAC channel2.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
+ * @param Data : Data to be loaded in the selected data holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)DAC_BASE;\r
+ tmp += DHR12R2_Offset + DAC_Align;\r
+\r
+ /* Set the DAC channel2 selected data holding register */\r
+ *(__IO uint32_t *)tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for dual channel\r
+ * DAC.\r
+ * @param DAC_Align: Specifies the data alignement for dual channel DAC.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data \r
+ * holding register.\r
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data \r
+ * holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)\r
+{\r
+ uint32_t data = 0, tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data1));\r
+ assert_param(IS_DAC_DATA(Data2));\r
+ \r
+ /* Calculate and set dual DAC data holding register value */\r
+ if (DAC_Align == DAC_Align_8b_R)\r
+ {\r
+ data = ((uint32_t)Data2 << 8) | Data1; \r
+ }\r
+ else\r
+ {\r
+ data = ((uint32_t)Data2 << 16) | Data1;\r
+ }\r
+ \r
+ tmp = (uint32_t)DAC_BASE;\r
+ tmp += DHR12RD_Offset + DAC_Align;\r
+\r
+ /* Set the dual DAC selected data holding register */\r
+ *(__IO uint32_t *)tmp = data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last data output value of the selected DAC cahnnel.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @retval The selected DAC channel data output value.\r
+ */\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ \r
+ tmp = (uint32_t) DAC_BASE ;\r
+ tmp += DOR_Offset + ((uint32_t)DAC_Channel >> 2);\r
+ \r
+ /* Returns the DAC channel data output register value */\r
+ return (uint16_t) (*(__IO uint32_t*) tmp);\r
+}\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
+/**\r
+ * @brief Checks whether the specified DAC flag is set or not.\r
+ * @param DAC_Channel: thee selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_FLAG: specifies the flag to check. \r
+ * This parameter can be only of the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r
+ * @retval The new state of DAC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Check the status of the specified DAC flag */\r
+ if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)\r
+ {\r
+ /* DAC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channelx's pending flags.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_FLAG: specifies the flag to clear. \r
+ * This parameter can be of the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r
+ * @retval None\r
+ */\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Clear the selected DAC flags */\r
+ DAC->SR = (DAC_FLAG << DAC_Channel);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DAC interrupt has occurred or not.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt source to check. \r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
+ * @retval The new state of DAC_IT (SET or RESET).\r
+ */\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT));\r
+\r
+ /* Get the DAC_IT enable bit status */\r
+ enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;\r
+ \r
+ /* Check the status of the specified DAC interrupt */\r
+ if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* DAC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channelx\92s interrupt pending bits.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt pending bit to clear.\r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
+ * @retval None\r
+ */\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ /* Clear the selected DAC interrupt pending bits */\r
+ DAC->SR = (DAC_IT << DAC_Channel);\r
+}\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
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