--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_cec.c\r
+ * @author MCD Application Team\r
+ * @version V3.3.0\r
+ * @date 04/16/2010\r
+ * @brief This file provides all the CEC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_cec.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC \r
+ * @brief CEC driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup CEC_Private_Defines\r
+ * @{\r
+ */ \r
+\r
+/* ------------ CEC registers bit address in the alias region ----------- */\r
+#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)\r
+\r
+/* --- CFGR Register ---*/\r
+\r
+/* Alias word address of PE bit */\r
+#define CFGR_OFFSET (CEC_OFFSET + 0x00)\r
+#define PE_BitNumber 0x00\r
+#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))\r
+\r
+/* Alias word address of IE bit */\r
+#define IE_BitNumber 0x01\r
+#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of TSOM bit */\r
+#define CSR_OFFSET (CEC_OFFSET + 0x10)\r
+#define TSOM_BitNumber 0x00\r
+#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))\r
+\r
+/* Alias word address of TEOM bit */\r
+#define TEOM_BitNumber 0x01\r
+#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))\r
+ \r
+#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */\r
+#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Private_Macros\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Private_Variables\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Deinitializes the CEC peripheral registers to their default reset \r
+ * values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CEC_DeInit(void)\r
+{\r
+ /* Enable CEC reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); \r
+ /* Release CEC from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); \r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the CEC peripheral according to the specified \r
+ * parameters in the CEC_InitStruct.\r
+ * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that\r
+ * contains the configuration information for the specified\r
+ * CEC peripheral.\r
+ * @retval None\r
+ */\r
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); \r
+ assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));\r
+ \r
+ /*---------------------------- CEC CFGR Configuration -----------------*/\r
+ /* Get the CEC CFGR value */\r
+ tmpreg = CEC->CFGR;\r
+ \r
+ /* Clear BTEM and BPEM bits */\r
+ tmpreg &= CFGR_CLEAR_Mask;\r
+ \r
+ /* Configure CEC: Bit Timing Error and Bit Period Error */\r
+ tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);\r
+\r
+ /* Write to CEC CFGR register*/\r
+ CEC->CFGR = tmpreg;\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified CEC peripheral.\r
+ * @param NewState: new state of the CEC peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void CEC_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;\r
+\r
+ if(NewState == DISABLE)\r
+ {\r
+ /* Wait until the PE bit is cleared by hardware (Idle Line detected) */\r
+ while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)\r
+ {\r
+ } \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CEC interrupt.\r
+ * @param NewState: new state of the CEC interrupt.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void CEC_ITConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Defines the Own Address of the CEC device.\r
+ * @param CEC_OwnAddress: The CEC own address\r
+ * @retval None\r
+ */\r
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));\r
+\r
+ /* Set the CEC own address */\r
+ CEC->OAR = CEC_OwnAddress;\r
+}\r
+\r
+/**\r
+ * @brief Sets the CEC prescaler value.\r
+ * @param CEC_Prescaler: CEC prescaler new value\r
+ * @retval None\r
+ */\r
+void CEC_SetPrescaler(uint16_t CEC_Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_PRESCALER(CEC_Prescaler));\r
+\r
+ /* Set the Prescaler value*/\r
+ CEC->PRES = CEC_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Transmits single data through the CEC peripheral.\r
+ * @param Data: the data to transmit.\r
+ * @retval None\r
+ */\r
+void CEC_SendDataByte(uint8_t Data)\r
+{ \r
+ /* Transmit Data */\r
+ CEC->TXD = Data ;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the CEC peripheral.\r
+ * @param None\r
+ * @retval The received data.\r
+ */\r
+uint8_t CEC_ReceiveDataByte(void)\r
+{\r
+ /* Receive Data */\r
+ return (uint8_t)(CEC->RXD);\r
+}\r
+\r
+/**\r
+ * @brief Starts a new message.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CEC_StartOfMessage(void)\r
+{ \r
+ /* Starts of new message */\r
+ *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;\r
+}\r
+\r
+/**\r
+ * @brief Transmits message with or without an EOM bit.\r
+ * @param NewState: new state of the CEC Tx End Of Message. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void CEC_EndOfMessageCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* The data byte will be transmitted with or without an EOM bit*/\r
+ *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Gets the CEC flag status\r
+ * @param CEC_FLAG: specifies the CEC flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg CEC_FLAG_BTE: Bit Timing Error\r
+ * @arg CEC_FLAG_BPE: Bit Period Error\r
+ * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error\r
+ * @arg CEC_FLAG_SBE: Start Bit Error\r
+ * @arg CEC_FLAG_ACKE: Block Acknowledge Error\r
+ * @arg CEC_FLAG_LINE: Line Error\r
+ * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error\r
+ * @arg CEC_FLAG_TEOM: Tx End Of Message \r
+ * @arg CEC_FLAG_TERR: Tx Error\r
+ * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished\r
+ * @arg CEC_FLAG_RSOM: Rx Start Of Message\r
+ * @arg CEC_FLAG_REOM: Rx End Of Message\r
+ * @arg CEC_FLAG_RERR: Rx Error\r
+ * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished\r
+ * @retval The new state of CEC_FLAG (SET or RESET)\r
+ */\r
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) \r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t cecreg = 0, cecbase = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_GET_FLAG(CEC_FLAG));\r
+ \r
+ /* Get the CEC peripheral base address */\r
+ cecbase = (uint32_t)(CEC_BASE);\r
+ \r
+ /* Read flag register index */\r
+ cecreg = CEC_FLAG >> 28;\r
+ \r
+ /* Get bit[23:0] of the flag */\r
+ CEC_FLAG &= FLAG_Mask;\r
+ \r
+ if(cecreg != 0)\r
+ {\r
+ /* Flag in CEC ESR Register */\r
+ CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);\r
+ \r
+ /* Get the CEC ESR register address */\r
+ cecbase += 0xC;\r
+ }\r
+ else\r
+ {\r
+ /* Get the CEC CSR register address */\r
+ cecbase += 0x10;\r
+ }\r
+ \r
+ if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* CEC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CEC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the CEC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CEC's pending flags.\r
+ * @param CEC_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg CEC_FLAG_TERR: Tx Error\r
+ * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished\r
+ * @arg CEC_FLAG_RSOM: Rx Start Of Message\r
+ * @arg CEC_FLAG_REOM: Rx End Of Message\r
+ * @arg CEC_FLAG_RERR: Rx Error\r
+ * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished\r
+ * @retval None\r
+ */\r
+void CEC_ClearFlag(uint32_t CEC_FLAG)\r
+{ \r
+ uint32_t tmp = 0x0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));\r
+\r
+ tmp = CEC->CSR & 0x2;\r
+ \r
+ /* Clear the selected CEC flags */\r
+ CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CEC interrupt has occurred or not.\r
+ * @param CEC_IT: specifies the CEC interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg CEC_IT_TERR: Tx Error\r
+ * @arg CEC_IT_TBTF: Tx Block Transfer Finished\r
+ * @arg CEC_IT_RERR: Rx Error\r
+ * @arg CEC_IT_RBTF: Rx Block Transfer Finished\r
+ * @retval The new state of CEC_IT (SET or RESET).\r
+ */\r
+ITStatus CEC_GetITStatus(uint8_t CEC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_GET_IT(CEC_IT));\r
+ \r
+ /* Get the CEC IT enable bit status */\r
+ enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;\r
+ \r
+ /* Check the status of the specified CEC interrupt */\r
+ if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* CEC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CEC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the CEC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CEC's interrupt pending bits.\r
+ * @param CEC_IT: specifies the CEC interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg CEC_IT_TERR: Tx Error\r
+ * @arg CEC_IT_TBTF: Tx Block Transfer Finished\r
+ * @arg CEC_IT_RERR: Rx Error\r
+ * @arg CEC_IT_RBTF: Rx Block Transfer Finished\r
+ * @retval None\r
+ */\r
+void CEC_ClearITPendingBit(uint16_t CEC_IT)\r
+{\r
+ uint32_t tmp = 0x0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_GET_IT(CEC_IT));\r
+ \r
+ tmp = CEC->CSR & 0x2;\r
+ \r
+ /* Clear the selected CEC interrupt pending bits */\r
+ CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
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