--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_can.c\r
+ * @author MCD Application Team\r
+ * @version V3.3.0\r
+ * @date 04/16/2010\r
+ * @brief This file provides all the CAN firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_can.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN \r
+ * @brief CAN driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup CAN_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* CAN Master Control Register bits */\r
+#define MCR_INRQ ((uint32_t)0x00000001) /* Initialization request */\r
+#define MCR_SLEEP ((uint32_t)0x00000002) /* Sleep mode request */\r
+#define MCR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO priority */\r
+#define MCR_RFLM ((uint32_t)0x00000008) /* Receive FIFO locked mode */\r
+#define MCR_NART ((uint32_t)0x00000010) /* No automatic retransmission */\r
+#define MCR_AWUM ((uint32_t)0x00000020) /* Automatic wake up mode */\r
+#define MCR_ABOM ((uint32_t)0x00000040) /* Automatic bus-off management */\r
+#define MCR_TTCM ((uint32_t)0x00000080) /* time triggered communication */\r
+#define MCR_RESET ((uint32_t)0x00008000) /* time triggered communication */\r
+#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */\r
+\r
+/* CAN Master Status Register bits */\r
+#define MSR_INAK ((uint32_t)0x00000001) /* Initialization acknowledge */\r
+#define MSR_WKUI ((uint32_t)0x00000008) /* Wake-up interrupt */\r
+#define MSR_SLAKI ((uint32_t)0x00000010) /* Sleep acknowledge interrupt */\r
+\r
+/* CAN Transmit Status Register bits */\r
+#define TSR_RQCP0 ((uint32_t)0x00000001) /* Request completed mailbox0 */\r
+#define TSR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of mailbox0 */\r
+#define TSR_ABRQ0 ((uint32_t)0x00000080) /* Abort request for mailbox0 */\r
+#define TSR_RQCP1 ((uint32_t)0x00000100) /* Request completed mailbox1 */\r
+#define TSR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of mailbox1 */\r
+#define TSR_ABRQ1 ((uint32_t)0x00008000) /* Abort request for mailbox1 */\r
+#define TSR_RQCP2 ((uint32_t)0x00010000) /* Request completed mailbox2 */\r
+#define TSR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of mailbox2 */\r
+#define TSR_ABRQ2 ((uint32_t)0x00800000) /* Abort request for mailbox2 */\r
+#define TSR_TME0 ((uint32_t)0x04000000) /* Transmit mailbox 0 empty */\r
+#define TSR_TME1 ((uint32_t)0x08000000) /* Transmit mailbox 1 empty */\r
+#define TSR_TME2 ((uint32_t)0x10000000) /* Transmit mailbox 2 empty */\r
+\r
+/* CAN Receive FIFO 0 Register bits */\r
+#define RF0R_FULL0 ((uint32_t)0x00000008) /* FIFO 0 full */\r
+#define RF0R_FOVR0 ((uint32_t)0x00000010) /* FIFO 0 overrun */\r
+#define RF0R_RFOM0 ((uint32_t)0x00000020) /* Release FIFO 0 output mailbox */\r
+\r
+/* CAN Receive FIFO 1 Register bits */\r
+#define RF1R_FULL1 ((uint32_t)0x00000008) /* FIFO 1 full */\r
+#define RF1R_FOVR1 ((uint32_t)0x00000010) /* FIFO 1 overrun */\r
+#define RF1R_RFOM1 ((uint32_t)0x00000020) /* Release FIFO 1 output mailbox */\r
+\r
+/* CAN Error Status Register bits */\r
+#define ESR_EWGF ((uint32_t)0x00000001) /* Error warning flag */\r
+#define ESR_EPVF ((uint32_t)0x00000002) /* Error passive flag */\r
+#define ESR_BOFF ((uint32_t)0x00000004) /* Bus-off flag */\r
+\r
+/* CAN Mailbox Transmit Request */\r
+#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */\r
+\r
+/* CAN Filter Master Register bits */\r
+#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */\r
+\r
+/* Time out for INAK bit */\r
+#define INAK_TimeOut ((uint32_t)0x0000FFFF)\r
+\r
+/* Time out for SLAK bit */\r
+#define SLAK_TimeOut ((uint32_t)0x0000FFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the CAN peripheral registers to their default reset values.\r
+ * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r
+ * @retval None.\r
+ */\r
+void CAN_DeInit(CAN_TypeDef* CANx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ \r
+ if (CANx == CAN1)\r
+ {\r
+ /* Enable CAN1 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);\r
+ /* Release CAN1 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);\r
+ }\r
+ else\r
+ { \r
+ /* Enable CAN2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);\r
+ /* Release CAN2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CAN peripheral according to the specified\r
+ * parameters in the CAN_InitStruct.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that\r
+ * contains the configuration information for the CAN peripheral.\r
+ * @retval Constant indicates initialization succeed which will be \r
+ * CANINITFAILED or CANINITOK.\r
+ */\r
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)\r
+{\r
+ uint8_t InitStatus = CANINITFAILED;\r
+ uint32_t wait_ack = 0x00000000;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));\r
+ assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));\r
+ assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));\r
+ assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));\r
+ assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));\r
+ assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));\r
+\r
+ /* exit from sleep mode */\r
+ CANx->MCR &= ~MCR_SLEEP;\r
+\r
+ /* Request initialisation */\r
+ CANx->MCR |= MCR_INRQ ;\r
+\r
+ /* Wait the acknowledge */\r
+ while (((CANx->MSR & MSR_INAK) != MSR_INAK) && (wait_ack != INAK_TimeOut))\r
+ {\r
+ wait_ack++;\r
+ }\r
+\r
+ /* ...and check acknowledged */\r
+ if ((CANx->MSR & MSR_INAK) != MSR_INAK)\r
+ {\r
+ InitStatus = CANINITFAILED;\r
+ }\r
+ else \r
+ {\r
+ /* Set the time triggered communication mode */\r
+ if (CAN_InitStruct->CAN_TTCM == ENABLE)\r
+ {\r
+ CANx->MCR |= MCR_TTCM;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~MCR_TTCM;\r
+ }\r
+\r
+ /* Set the automatic bus-off management */\r
+ if (CAN_InitStruct->CAN_ABOM == ENABLE)\r
+ {\r
+ CANx->MCR |= MCR_ABOM;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~MCR_ABOM;\r
+ }\r
+\r
+ /* Set the automatic wake-up mode */\r
+ if (CAN_InitStruct->CAN_AWUM == ENABLE)\r
+ {\r
+ CANx->MCR |= MCR_AWUM;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~MCR_AWUM;\r
+ }\r
+\r
+ /* Set the no automatic retransmission */\r
+ if (CAN_InitStruct->CAN_NART == ENABLE)\r
+ {\r
+ CANx->MCR |= MCR_NART;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~MCR_NART;\r
+ }\r
+\r
+ /* Set the receive FIFO locked mode */\r
+ if (CAN_InitStruct->CAN_RFLM == ENABLE)\r
+ {\r
+ CANx->MCR |= MCR_RFLM;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~MCR_RFLM;\r
+ }\r
+\r
+ /* Set the transmit FIFO priority */\r
+ if (CAN_InitStruct->CAN_TXFP == ENABLE)\r
+ {\r
+ CANx->MCR |= MCR_TXFP;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~MCR_TXFP;\r
+ }\r
+\r
+ /* Set the bit timing register */\r
+ CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) |\r
+ ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) |\r
+ ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);\r
+\r
+ /* Request leave initialisation */\r
+ CANx->MCR &= ~MCR_INRQ;\r
+\r
+ /* Wait the acknowledge */\r
+ wait_ack = 0x00;\r
+\r
+ while (((CANx->MSR & MSR_INAK) == MSR_INAK) && (wait_ack != INAK_TimeOut))\r
+ {\r
+ wait_ack++;\r
+ }\r
+\r
+ /* ...and check acknowledged */\r
+ if ((CANx->MSR & MSR_INAK) == MSR_INAK)\r
+ {\r
+ InitStatus = CANINITFAILED;\r
+ }\r
+ else\r
+ {\r
+ InitStatus = CANINITOK ;\r
+ }\r
+ }\r
+\r
+ /* At this step, return the status of initialization */\r
+ return InitStatus;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CAN peripheral according to the specified\r
+ * parameters in the CAN_FilterInitStruct.\r
+ * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef\r
+ * structure that contains the configuration information.\r
+ * @retval None.\r
+ */\r
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)\r
+{\r
+ uint32_t filter_number_bit_pos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));\r
+ assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));\r
+ assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));\r
+ assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));\r
+\r
+ filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber;\r
+\r
+ /* Initialisation mode for the filter */\r
+ CAN1->FMR |= FMR_FINIT;\r
+\r
+ /* Filter Deactivation */\r
+ CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;\r
+\r
+ /* Filter Scale */\r
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)\r
+ {\r
+ /* 16-bit scale for the filter */\r
+ CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;\r
+\r
+ /* First 16-bit identifier and First 16-bit mask */\r
+ /* Or First 16-bit identifier and Second 16-bit identifier */\r
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |\r
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);\r
+\r
+ /* Second 16-bit identifier and Second 16-bit mask */\r
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */\r
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);\r
+ }\r
+\r
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)\r
+ {\r
+ /* 32-bit scale for the filter */\r
+ CAN1->FS1R |= filter_number_bit_pos;\r
+ /* 32-bit identifier or First 32-bit identifier */\r
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);\r
+ /* 32-bit mask or Second 32-bit identifier */\r
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);\r
+ }\r
+\r
+ /* Filter Mode */\r
+ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)\r
+ {\r
+ /*Id/Mask mode for the filter*/\r
+ CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;\r
+ }\r
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\r
+ {\r
+ /*Identifier list mode for the filter*/\r
+ CAN1->FM1R |= (uint32_t)filter_number_bit_pos;\r
+ }\r
+\r
+ /* Filter FIFO assignment */\r
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)\r
+ {\r
+ /* FIFO 0 assignation for the filter */\r
+ CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;\r
+ }\r
+\r
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)\r
+ {\r
+ /* FIFO 1 assignation for the filter */\r
+ CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;\r
+ }\r
+ \r
+ /* Filter activation */\r
+ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)\r
+ {\r
+ CAN1->FA1R |= filter_number_bit_pos;\r
+ }\r
+\r
+ /* Leave the initialisation mode for the filter */\r
+ CAN1->FMR &= ~FMR_FINIT;\r
+}\r
+\r
+/**\r
+ * @brief Fills each CAN_InitStruct member with its default value.\r
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None.\r
+ */\r
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)\r
+{\r
+ /* Reset CAN init structure parameters values */\r
+ /* Initialize the time triggered communication mode */\r
+ CAN_InitStruct->CAN_TTCM = DISABLE;\r
+ /* Initialize the automatic bus-off management */\r
+ CAN_InitStruct->CAN_ABOM = DISABLE;\r
+ /* Initialize the automatic wake-up mode */\r
+ CAN_InitStruct->CAN_AWUM = DISABLE;\r
+ /* Initialize the no automatic retransmission */\r
+ CAN_InitStruct->CAN_NART = DISABLE;\r
+ /* Initialize the receive FIFO locked mode */\r
+ CAN_InitStruct->CAN_RFLM = DISABLE;\r
+ /* Initialize the transmit FIFO priority */\r
+ CAN_InitStruct->CAN_TXFP = DISABLE;\r
+ /* Initialize the CAN_Mode member */\r
+ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;\r
+ /* Initialize the CAN_SJW member */\r
+ CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;\r
+ /* Initialize the CAN_BS1 member */\r
+ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;\r
+ /* Initialize the CAN_BS2 member */\r
+ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;\r
+ /* Initialize the CAN_Prescaler member */\r
+ CAN_InitStruct->CAN_Prescaler = 1;\r
+}\r
+\r
+/**\r
+ * @brief Select the start bank filter for slave CAN.\r
+ * @note This function applies only to STM32 Connectivity line devices.\r
+ * @param CAN_BankNumber: Select the start slave bank filter from 1..27.\r
+ * @retval None.\r
+ */\r
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));\r
+ /* enter Initialisation mode for the filter */\r
+ CAN1->FMR |= FMR_FINIT;\r
+ /* Select the start slave bank */\r
+ CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;\r
+ CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;\r
+ /* Leave Initialisation mode for the filter */\r
+ CAN1->FMR &= ~FMR_FINIT;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified CAN interrupts.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.\r
+ * This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0,\r
+ * CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1,\r
+ * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV,\r
+ * CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or\r
+ * CAN_IT_SLK.\r
+ * @param NewState: new state of the CAN interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_ITConfig(CAN_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected CAN interrupt */\r
+ CANx->IER |= CAN_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected CAN interrupt */\r
+ CANx->IER &= ~CAN_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initiates the transmission of a message.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param TxMessage: pointer to a structure which contains CAN Id, CAN\r
+ * DLC and CAN datas.\r
+ * @retval The number of the mailbox that is used for transmission\r
+ * or CAN_NO_MB if there is no empty mailbox.\r
+ */\r
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)\r
+{\r
+ uint8_t transmit_mailbox = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_IDTYPE(TxMessage->IDE));\r
+ assert_param(IS_CAN_RTR(TxMessage->RTR));\r
+ assert_param(IS_CAN_DLC(TxMessage->DLC));\r
+\r
+ /* Select one empty transmit mailbox */\r
+ if ((CANx->TSR&TSR_TME0) == TSR_TME0)\r
+ {\r
+ transmit_mailbox = 0;\r
+ }\r
+ else if ((CANx->TSR&TSR_TME1) == TSR_TME1)\r
+ {\r
+ transmit_mailbox = 1;\r
+ }\r
+ else if ((CANx->TSR&TSR_TME2) == TSR_TME2)\r
+ {\r
+ transmit_mailbox = 2;\r
+ }\r
+ else\r
+ {\r
+ transmit_mailbox = CAN_NO_MB;\r
+ }\r
+\r
+ if (transmit_mailbox != CAN_NO_MB)\r
+ {\r
+ /* Set up the Id */\r
+ CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;\r
+ if (TxMessage->IDE == CAN_ID_STD)\r
+ {\r
+ assert_param(IS_CAN_STDID(TxMessage->StdId)); \r
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR);\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_CAN_EXTID(TxMessage->ExtId));\r
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE | \r
+ TxMessage->RTR);\r
+ }\r
+ \r
+\r
+ /* Set up the DLC */\r
+ TxMessage->DLC &= (uint8_t)0x0000000F;\r
+ CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;\r
+ CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;\r
+\r
+ /* Set up the data field */\r
+ CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | \r
+ ((uint32_t)TxMessage->Data[2] << 16) |\r
+ ((uint32_t)TxMessage->Data[1] << 8) | \r
+ ((uint32_t)TxMessage->Data[0]));\r
+ CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | \r
+ ((uint32_t)TxMessage->Data[6] << 16) |\r
+ ((uint32_t)TxMessage->Data[5] << 8) |\r
+ ((uint32_t)TxMessage->Data[4]));\r
+ /* Request transmission */\r
+ CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;\r
+ }\r
+ return transmit_mailbox;\r
+}\r
+\r
+/**\r
+ * @brief Checks the transmission of a message.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param TransmitMailbox: the number of the mailbox that is used for transmission.\r
+ * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case.\r
+ */\r
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)\r
+{\r
+ /* RQCP, TXOK and TME bits */\r
+ uint8_t state = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));\r
+ switch (TransmitMailbox)\r
+ {\r
+ case (0): state |= (uint8_t)((CANx->TSR & TSR_RQCP0) << 2);\r
+ state |= (uint8_t)((CANx->TSR & TSR_TXOK0) >> 0);\r
+ state |= (uint8_t)((CANx->TSR & TSR_TME0) >> 26);\r
+ break;\r
+ case (1): state |= (uint8_t)((CANx->TSR & TSR_RQCP1) >> 6);\r
+ state |= (uint8_t)((CANx->TSR & TSR_TXOK1) >> 8);\r
+ state |= (uint8_t)((CANx->TSR & TSR_TME1) >> 27);\r
+ break;\r
+ case (2): state |= (uint8_t)((CANx->TSR & TSR_RQCP2) >> 14);\r
+ state |= (uint8_t)((CANx->TSR & TSR_TXOK2) >> 16);\r
+ state |= (uint8_t)((CANx->TSR & TSR_TME2) >> 28);\r
+ break;\r
+ default:\r
+ state = CANTXFAILED;\r
+ break;\r
+ }\r
+ switch (state)\r
+ {\r
+ /* transmit pending */\r
+ case (0x0): state = CANTXPENDING;\r
+ break;\r
+ /* transmit failed */\r
+ case (0x5): state = CANTXFAILED;\r
+ break;\r
+ /* transmit succedeed */\r
+ case (0x7): state = CANTXOK;\r
+ break;\r
+ default:\r
+ state = CANTXFAILED;\r
+ break;\r
+ }\r
+ return state;\r
+}\r
+\r
+/**\r
+ * @brief Cancels a transmit request.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. \r
+ * @param Mailbox: Mailbox number.\r
+ * @retval None.\r
+ */\r
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));\r
+ /* abort transmission */\r
+ switch (Mailbox)\r
+ {\r
+ case (0): CANx->TSR |= TSR_ABRQ0;\r
+ break;\r
+ case (1): CANx->TSR |= TSR_ABRQ1;\r
+ break;\r
+ case (2): CANx->TSR |= TSR_ABRQ2;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Releases a FIFO.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. \r
+ * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.\r
+ * @retval None.\r
+ */\r
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ /* Release FIFO0 */\r
+ if (FIFONumber == CAN_FIFO0)\r
+ {\r
+ CANx->RF0R = RF0R_RFOM0;\r
+ }\r
+ /* Release FIFO1 */\r
+ else /* FIFONumber == CAN_FIFO1 */\r
+ {\r
+ CANx->RF1R = RF1R_RFOM1;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the number of pending messages.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
+ * @retval NbMessage which is the number of pending message.\r
+ */\r
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)\r
+{\r
+ uint8_t message_pending=0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ if (FIFONumber == CAN_FIFO0)\r
+ {\r
+ message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);\r
+ }\r
+ else if (FIFONumber == CAN_FIFO1)\r
+ {\r
+ message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);\r
+ }\r
+ else\r
+ {\r
+ message_pending = 0;\r
+ }\r
+ return message_pending;\r
+}\r
+\r
+/**\r
+ * @brief Receives a message.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
+ * @param RxMessage: pointer to a structure receive message which \r
+ * contains CAN Id, CAN DLC, CAN datas and FMI number.\r
+ * @retval None.\r
+ */\r
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ /* Get the Id */\r
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;\r
+ if (RxMessage->IDE == CAN_ID_STD)\r
+ {\r
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);\r
+ }\r
+ else\r
+ {\r
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);\r
+ }\r
+ \r
+ RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;\r
+ /* Get the DLC */\r
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;\r
+ /* Get the FMI */\r
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);\r
+ /* Get the data field */\r
+ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;\r
+ RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);\r
+ RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);\r
+ RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);\r
+ RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;\r
+ RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);\r
+ RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);\r
+ RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);\r
+ /* Release the FIFO */\r
+ CAN_FIFORelease(CANx, FIFONumber);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DBG Freeze for CAN.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param NewState: new state of the CAN peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable Debug Freeze */\r
+ CANx->MCR |= MCR_DBF;\r
+ }\r
+ else\r
+ {\r
+ /* Disable Debug Freeze */\r
+ CANx->MCR &= ~MCR_DBF;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters the low power mode.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.\r
+ */\r
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)\r
+{\r
+ uint8_t sleepstatus = CANSLEEPFAILED;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ \r
+ /* Request Sleep mode */\r
+ CANx->MCR = (((CANx->MCR) & (uint32_t)(~MCR_INRQ)) | MCR_SLEEP);\r
+ \r
+ /* Sleep mode status */\r
+ if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)\r
+ {\r
+ /* Sleep mode not entered */\r
+ sleepstatus = CANSLEEPOK;\r
+ }\r
+ /* At this step, sleep mode status */\r
+ return (uint8_t)sleepstatus;\r
+}\r
+\r
+/**\r
+ * @brief Wakes the CAN up.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.\r
+ */\r
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)\r
+{\r
+ uint32_t wait_slak = SLAK_TimeOut ;\r
+ uint8_t wakeupstatus = CANWAKEUPFAILED;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ \r
+ /* Wake up request */\r
+ CANx->MCR &= ~MCR_SLEEP;\r
+ \r
+ /* Sleep mode status */\r
+ while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))\r
+ {\r
+ wait_slak--;\r
+ }\r
+ if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)\r
+ {\r
+ /* Sleep mode exited */\r
+ wakeupstatus = CANWAKEUPOK;\r
+ }\r
+ /* At this step, sleep mode status */\r
+ return (uint8_t)wakeupstatus;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CAN flag is set or not.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_FLAG: specifies the flag to check.\r
+ * This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or CAN_FLAG_BOF.\r
+ * @retval The new state of CAN_FLAG (SET or RESET).\r
+ */\r
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_FLAG(CAN_FLAG));\r
+ /* Check the status of the specified CAN flag */\r
+ if ((CANx->ESR & CAN_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the CAN_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CAN's pending flags.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_FLAG: specifies the flag to clear.\r
+ * @retval None.\r
+ */\r
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_FLAG(CAN_FLAG));\r
+ /* Clear the selected CAN flags */\r
+ CANx->ESR &= ~CAN_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CAN interrupt has occurred or not.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_IT: specifies the CAN interrupt source to check.\r
+ * This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2,\r
+ * CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1,\r
+ * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, \r
+ * CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK.\r
+ * @retval The new state of CAN_IT (SET or RESET).\r
+ */\r
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_ITStatus(CAN_IT));\r
+ switch (CAN_IT)\r
+ {\r
+ case CAN_IT_RQCP0:\r
+ pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP0);\r
+ break;\r
+ case CAN_IT_RQCP1:\r
+ pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP1);\r
+ break;\r
+ case CAN_IT_RQCP2:\r
+ pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP2);\r
+ break;\r
+ case CAN_IT_FF0:\r
+ pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FULL0);\r
+ break;\r
+ case CAN_IT_FOV0:\r
+ pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FOVR0);\r
+ break;\r
+ case CAN_IT_FF1:\r
+ pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FULL1);\r
+ break;\r
+ case CAN_IT_FOV1:\r
+ pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FOVR1);\r
+ break;\r
+ case CAN_IT_EWG:\r
+ pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EWGF);\r
+ break;\r
+ case CAN_IT_EPV:\r
+ pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EPVF);\r
+ break;\r
+ case CAN_IT_BOF:\r
+ pendingbitstatus = CheckITStatus(CANx->ESR, ESR_BOFF);\r
+ break;\r
+ case CAN_IT_SLK:\r
+ pendingbitstatus = CheckITStatus(CANx->MSR, MSR_SLAKI);\r
+ break;\r
+ case CAN_IT_WKU:\r
+ pendingbitstatus = CheckITStatus(CANx->MSR, MSR_WKUI);\r
+ break;\r
+ default :\r
+ pendingbitstatus = RESET;\r
+ break;\r
+ }\r
+ /* Return the CAN_IT status */\r
+ return pendingbitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CAN\92s interrupt pending bits.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_IT: specifies the interrupt pending bit to clear.\r
+ * @retval None.\r
+ */\r
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_ITStatus(CAN_IT));\r
+ switch (CAN_IT)\r
+ {\r
+ case CAN_IT_RQCP0:\r
+ CANx->TSR = TSR_RQCP0; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_RQCP1:\r
+ CANx->TSR = TSR_RQCP1; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_RQCP2:\r
+ CANx->TSR = TSR_RQCP2; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_FF0:\r
+ CANx->RF0R = RF0R_FULL0; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_FOV0:\r
+ CANx->RF0R = RF0R_FOVR0; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_FF1:\r
+ CANx->RF1R = RF1R_FULL1; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_FOV1:\r
+ CANx->RF1R = RF1R_FOVR1; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_EWG:\r
+ CANx->ESR &= ~ ESR_EWGF; /* rw */\r
+ break;\r
+ case CAN_IT_EPV:\r
+ CANx->ESR &= ~ ESR_EPVF; /* rw */\r
+ break;\r
+ case CAN_IT_BOF:\r
+ CANx->ESR &= ~ ESR_BOFF; /* rw */\r
+ break;\r
+ case CAN_IT_WKU:\r
+ CANx->MSR = MSR_WKUI; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_SLK:\r
+ CANx->MSR = MSR_SLAKI; /* rc_w1*/\r
+ break;\r
+ default :\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the CAN interrupt has occurred or not.\r
+ * @param CAN_Reg: specifies the CAN interrupt register to check.\r
+ * @param It_Bit: specifies the interrupt source bit to check.\r
+ * @retval The new state of the CAN Interrupt (SET or RESET).\r
+ */\r
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+ \r
+ if ((CAN_Reg & It_Bit) != (uint32_t)RESET)\r
+ {\r
+ /* CAN_IT is set */\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAN_IT is reset */\r
+ pendingbitstatus = RESET;\r
+ }\r
+ return pendingbitstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff