--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_syscfg.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the SYSCFG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/*!< Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_SYSCFG_H\r
+#define __STM32L1xx_SYSCFG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*!< Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SYSCFG\r
+ * @{\r
+ */ \r
+ \r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SYSCFG_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup EXTI_Port_Sources \r
+ * @{\r
+ */ \r
+#define EXTI_PortSourceGPIOA ((uint8_t)0x00)\r
+#define EXTI_PortSourceGPIOB ((uint8_t)0x01)\r
+#define EXTI_PortSourceGPIOC ((uint8_t)0x02)\r
+#define EXTI_PortSourceGPIOD ((uint8_t)0x03)\r
+#define EXTI_PortSourceGPIOE ((uint8_t)0x04)\r
+#define EXTI_PortSourceGPIOH ((uint8_t)0x05)\r
+ \r
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOH)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Pin_sources \r
+ * @{\r
+ */ \r
+#define EXTI_PinSource0 ((uint8_t)0x00)\r
+#define EXTI_PinSource1 ((uint8_t)0x01)\r
+#define EXTI_PinSource2 ((uint8_t)0x02)\r
+#define EXTI_PinSource3 ((uint8_t)0x03)\r
+#define EXTI_PinSource4 ((uint8_t)0x04)\r
+#define EXTI_PinSource5 ((uint8_t)0x05)\r
+#define EXTI_PinSource6 ((uint8_t)0x06)\r
+#define EXTI_PinSource7 ((uint8_t)0x07)\r
+#define EXTI_PinSource8 ((uint8_t)0x08)\r
+#define EXTI_PinSource9 ((uint8_t)0x09)\r
+#define EXTI_PinSource10 ((uint8_t)0x0A)\r
+#define EXTI_PinSource11 ((uint8_t)0x0B)\r
+#define EXTI_PinSource12 ((uint8_t)0x0C)\r
+#define EXTI_PinSource13 ((uint8_t)0x0D)\r
+#define EXTI_PinSource14 ((uint8_t)0x0E)\r
+#define EXTI_PinSource15 ((uint8_t)0x0F)\r
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \\r
+ ((PINSOURCE) == EXTI_PinSource1) || \\r
+ ((PINSOURCE) == EXTI_PinSource2) || \\r
+ ((PINSOURCE) == EXTI_PinSource3) || \\r
+ ((PINSOURCE) == EXTI_PinSource4) || \\r
+ ((PINSOURCE) == EXTI_PinSource5) || \\r
+ ((PINSOURCE) == EXTI_PinSource6) || \\r
+ ((PINSOURCE) == EXTI_PinSource7) || \\r
+ ((PINSOURCE) == EXTI_PinSource8) || \\r
+ ((PINSOURCE) == EXTI_PinSource9) || \\r
+ ((PINSOURCE) == EXTI_PinSource10) || \\r
+ ((PINSOURCE) == EXTI_PinSource11) || \\r
+ ((PINSOURCE) == EXTI_PinSource12) || \\r
+ ((PINSOURCE) == EXTI_PinSource13) || \\r
+ ((PINSOURCE) == EXTI_PinSource14) || \\r
+ ((PINSOURCE) == EXTI_PinSource15))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Memory_Remap_Config \r
+ * @{\r
+ */ \r
+#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)\r
+#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)\r
+#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)\r
+ \r
+#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_SRAM))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RI_Resistor\r
+ * @{\r
+ */\r
+\r
+#define RI_Resistor_10KPU COMP_CSR_10KPU\r
+#define RI_Resistor_400KPU COMP_CSR_400KPU\r
+#define RI_Resistor_10KPD COMP_CSR_10KPD\r
+#define RI_Resistor_400KPD COMP_CSR_400KPD\r
+\r
+#define IS_RI_RESISTOR(RESISTOR) (((RESISTOR) == COMP_CSR_10KPU) || \\r
+ ((RESISTOR) == COMP_CSR_400KPU) || \\r
+ ((RESISTOR) == COMP_CSR_10KPD) || \\r
+ ((RESISTOR) == COMP_CSR_400KPD))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RI_InputCapture\r
+ * @{\r
+ */ \r
+ \r
+#define RI_InputCapture_IC1 RI_ICR_IC1 /*!< Input Capture 1 */\r
+#define RI_InputCapture_IC2 RI_ICR_IC2 /*!< Input Capture 2 */\r
+#define RI_InputCapture_IC3 RI_ICR_IC3 /*!< Input Capture 3 */\r
+#define RI_InputCapture_IC4 RI_ICR_IC4 /*!< Input Capture 4 */\r
+\r
+#define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup TIM_Select\r
+ * @{\r
+ */ \r
+ \r
+#define TIM_Select_None ((uint32_t)0x00000000) /*!< None selected */\r
+#define TIM_Select_TIM2 ((uint32_t)0x00010000) /*!< Timer 2 selected */\r
+#define TIM_Select_TIM3 ((uint32_t)0x00020000) /*!< Timer 3 selected */\r
+#define TIM_Select_TIM4 ((uint32_t)0x00030000) /*!< Timer 4 selected */\r
+\r
+#define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \\r
+ ((TIM) == TIM_Select_TIM2) || \\r
+ ((TIM) == TIM_Select_TIM3) || \\r
+ ((TIM) == TIM_Select_TIM4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RI_InputCaptureRouting\r
+ * @{\r
+ */ \r
+ /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ \r
+#define RI_InputCaptureRouting_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */\r
+#define RI_InputCaptureRouting_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */\r
+#define RI_InputCaptureRouting_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */\r
+#define RI_InputCaptureRouting_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */\r
+#define RI_InputCaptureRouting_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */\r
+#define RI_InputCaptureRouting_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */\r
+#define RI_InputCaptureRouting_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */\r
+#define RI_InputCaptureRouting_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */\r
+#define RI_InputCaptureRouting_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */\r
+#define RI_InputCaptureRouting_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */\r
+#define RI_InputCaptureRouting_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */\r
+#define RI_InputCaptureRouting_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */\r
+#define RI_InputCaptureRouting_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */\r
+#define RI_InputCaptureRouting_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */\r
+#define RI_InputCaptureRouting_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */\r
+#define RI_InputCaptureRouting_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */\r
+\r
+#define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_1) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_2) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_3) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_4) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_5) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_6) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_7) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_8) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_9) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_10) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_11) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_12) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_13) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_14) || \\r
+ ((ROUTING) == RI_InputCaptureRouting_15))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RI_IOSwitch\r
+ * @{\r
+ */ \r
+ \r
+/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */\r
+#define RI_IOSwitch_CH0 ((uint32_t)0x80000001)\r
+#define RI_IOSwitch_CH1 ((uint32_t)0x80000002)\r
+#define RI_IOSwitch_CH2 ((uint32_t)0x80000004)\r
+#define RI_IOSwitch_CH3 ((uint32_t)0x80000008)\r
+#define RI_IOSwitch_CH4 ((uint32_t)0x80000010)\r
+#define RI_IOSwitch_CH5 ((uint32_t)0x80000020)\r
+#define RI_IOSwitch_CH6 ((uint32_t)0x80000040)\r
+#define RI_IOSwitch_CH7 ((uint32_t)0x80000080)\r
+#define RI_IOSwitch_CH8 ((uint32_t)0x80000100)\r
+#define RI_IOSwitch_CH9 ((uint32_t)0x80000200)\r
+#define RI_IOSwitch_CH10 ((uint32_t)0x80000400)\r
+#define RI_IOSwitch_CH11 ((uint32_t)0x80000800)\r
+#define RI_IOSwitch_CH12 ((uint32_t)0x80001000)\r
+#define RI_IOSwitch_CH13 ((uint32_t)0x80002000)\r
+#define RI_IOSwitch_CH14 ((uint32_t)0x80004000)\r
+#define RI_IOSwitch_CH15 ((uint32_t)0x80008000)\r
+#define RI_IOSwitch_CH18 ((uint32_t)0x80040000)\r
+#define RI_IOSwitch_CH19 ((uint32_t)0x80080000)\r
+#define RI_IOSwitch_CH20 ((uint32_t)0x80100000)\r
+#define RI_IOSwitch_CH21 ((uint32_t)0x80200000)\r
+#define RI_IOSwitch_CH22 ((uint32_t)0x80400000)\r
+#define RI_IOSwitch_CH23 ((uint32_t)0x80800000)\r
+#define RI_IOSwitch_CH24 ((uint32_t)0x81000000)\r
+#define RI_IOSwitch_CH25 ((uint32_t)0x82000000)\r
+#define RI_IOSwitch_VCOMP ((uint32_t)0x84000000) /* VCOMP is an internal switch used to connect \r
+ selected channel to COMP1 non inverting input */\r
+\r
+/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ \r
+#define RI_IOSwitch_GR10_1 ((uint32_t)0x00000001)\r
+#define RI_IOSwitch_GR10_2 ((uint32_t)0x00000002)\r
+#define RI_IOSwitch_GR10_3 ((uint32_t)0x00000004)\r
+#define RI_IOSwitch_GR10_4 ((uint32_t)0x00000008)\r
+#define RI_IOSwitch_GR6_1 ((uint32_t)0x00000010)\r
+#define RI_IOSwitch_GR6_2 ((uint32_t)0x00000020)\r
+#define RI_IOSwitch_GR5_1 ((uint32_t)0x00000040)\r
+#define RI_IOSwitch_GR5_2 ((uint32_t)0x00000080)\r
+#define RI_IOSwitch_GR5_3 ((uint32_t)0x00000100)\r
+#define RI_IOSwitch_GR4_1 ((uint32_t)0x00000200)\r
+#define RI_IOSwitch_GR4_2 ((uint32_t)0x00000400)\r
+#define RI_IOSwitch_GR4_3 ((uint32_t)0x00000800)\r
+\r
+#define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH4) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH5) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH6) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH7) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH8) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH9) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH10) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH11) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH12) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH13) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH14) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH15) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH18) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH19) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH20) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH21) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH22) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH23) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH24) || \\r
+ ((IOSWITCH) == RI_IOSwitch_CH25) || \\r
+ ((IOSWITCH) == RI_IOSwitch_VCOMP) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR10_4) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR6_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR6_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR5_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR5_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR5_3) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR4_1) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR4_2) || \\r
+ ((IOSWITCH) == RI_IOSwitch_GR4_3))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Port\r
+ * @{\r
+ */\r
+\r
+#define RI_PortA ((uint8_t)0x01) /*!< GPIOA selected */\r
+#define RI_PortB ((uint8_t)0x02) /*!< GPIOB selected */\r
+#define RI_PortC ((uint8_t)0x03) /*!< GPIOC selected */\r
+#define RI_PortD ((uint8_t)0x04) /*!< GPIOD selected */\r
+#define RI_PortE ((uint8_t)0x05) /*!< GPIOE selected */\r
+\r
+#define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \\r
+ ((PORT) == RI_PortB) || \\r
+ ((PORT) == RI_PortC) || \\r
+ ((PORT) == RI_PortD) || \\r
+ ((PORT) == RI_PortE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Pin define \r
+ * @{\r
+ */\r
+#define RI_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
+#define RI_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
+#define RI_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
+#define RI_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
+#define RI_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
+#define RI_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
+#define RI_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
+#define RI_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
+#define RI_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
+#define RI_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
+#define RI_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
+#define RI_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
+#define RI_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
+#define RI_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
+#define RI_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
+#define RI_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
+#define RI_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */\r
+\r
+#define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the RTC configuration to the default reset state *****/\r
+void SYSCFG_DeInit(void);\r
+void SYSCFG_RIDeInit(void);\r
+\r
+/* SYSCFG Initialization and Configuration functions **************************/ \r
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);\r
+void SYSCFG_USBPuCmd(FunctionalState NewState);\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);\r
+\r
+/* RI Initialization and Configuration functions ******************************/ \r
+void SYSCFG_RITIMSelect(uint32_t TIM_Select);\r
+void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting);\r
+void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState);\r
+void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState);\r
+void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState);\r
+void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,\r
+ FunctionalState NewState);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_SYSCFG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff