--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_rcc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the RCC \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_RCC_H\r
+#define __STM32L1xx_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+typedef struct\r
+{\r
+ uint32_t SYSCLK_Frequency;\r
+ uint32_t HCLK_Frequency;\r
+ uint32_t PCLK1_Frequency;\r
+ uint32_t PCLK2_Frequency;\r
+}RCC_ClocksTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HSE_configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_HSE_OFF ((uint8_t)0x00)\r
+#define RCC_HSE_ON ((uint8_t)0x01)\r
+#define RCC_HSE_Bypass ((uint8_t)0x05)\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+ ((HSE) == RCC_HSE_Bypass))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup MSI_Clock_Range \r
+ * @{\r
+ */\r
+\r
+#define RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */\r
+#define RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */\r
+#define RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */\r
+#define RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */\r
+#define RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */\r
+#define RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */\r
+#define RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */\r
+\r
+#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_0) || \\r
+ ((RANGE) == RCC_MSIRange_1) || \\r
+ ((RANGE) == RCC_MSIRange_2) || \\r
+ ((RANGE) == RCC_MSIRange_3) || \\r
+ ((RANGE) == RCC_MSIRange_4) || \\r
+ ((RANGE) == RCC_MSIRange_5) || \\r
+ ((RANGE) == RCC_MSIRange_6))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup PLL_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLSource_HSI ((uint8_t)0x00)\r
+#define RCC_PLLSource_HSE ((uint8_t)0x01)\r
+\r
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \\r
+ ((SOURCE) == RCC_PLLSource_HSE))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup PLL_Multiplication_Factor \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLMul_3 ((uint8_t)0x00)\r
+#define RCC_PLLMul_4 ((uint8_t)0x04)\r
+#define RCC_PLLMul_6 ((uint8_t)0x08)\r
+#define RCC_PLLMul_8 ((uint8_t)0x0C)\r
+#define RCC_PLLMul_12 ((uint8_t)0x10)\r
+#define RCC_PLLMul_16 ((uint8_t)0x14)\r
+#define RCC_PLLMul_24 ((uint8_t)0x18)\r
+#define RCC_PLLMul_32 ((uint8_t)0x1C)\r
+#define RCC_PLLMul_48 ((uint8_t)0x20)\r
+\r
+\r
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \\r
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \\r
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \\r
+ ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \\r
+ ((MUL) == RCC_PLLMul_48))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PLL_Divider_Factor \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLDiv_2 ((uint8_t)0x40)\r
+#define RCC_PLLDiv_3 ((uint8_t)0x80)\r
+#define RCC_PLLDiv_4 ((uint8_t)0xC0)\r
+\r
+\r
+#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \\r
+ ((DIV) == RCC_PLLDiv_4))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup System_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI\r
+#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI\r
+#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE\r
+#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL\r
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_HSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AHB_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1\r
+#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2\r
+#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4\r
+#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8\r
+#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16\r
+#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64\r
+#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128\r
+#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256\r
+#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\r
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\r
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\r
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\r
+ ((HCLK) == RCC_SYSCLK_Div512))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup APB1_APB2_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1\r
+#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2\r
+#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4\r
+#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8\r
+#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\r
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\r
+ ((PCLK) == RCC_HCLK_Div16))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/** @defgroup RCC_Interrupt_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_IT_LSIRDY ((uint8_t)0x01)\r
+#define RCC_IT_LSERDY ((uint8_t)0x02)\r
+#define RCC_IT_HSIRDY ((uint8_t)0x04)\r
+#define RCC_IT_HSERDY ((uint8_t)0x08)\r
+#define RCC_IT_PLLRDY ((uint8_t)0x10)\r
+#define RCC_IT_MSIRDY ((uint8_t)0x20)\r
+#define RCC_IT_CSS ((uint8_t)0x80)\r
+\r
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \\r
+ ((IT) == RCC_IT_CSS))\r
+\r
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LSE_Configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_LSE_OFF ((uint8_t)0x00)\r
+#define RCC_LSE_ON ((uint8_t)0x01)\r
+#define RCC_LSE_Bypass ((uint8_t)0x05)\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+ ((LSE) == RCC_LSE_Bypass))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE\r
+#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI\r
+#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE\r
+#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)\r
+#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)\r
+#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)\r
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div16))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AHB_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN\r
+#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN\r
+#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN\r
+#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN\r
+#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN\r
+#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN\r
+#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN\r
+#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN\r
+#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN\r
+#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN\r
+\r
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEFF6FC0) == 0x00) && ((PERIPH) != 0x00))\r
+#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xFEFE6FC0) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup APB2_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN\r
+#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN\r
+#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN\r
+#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN\r
+#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN\r
+#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN\r
+#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN\r
+\r
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFADE2) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup APB1_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN\r
+#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN\r
+#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN\r
+#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN\r
+#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN\r
+#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN\r
+#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN\r
+#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN\r
+#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN\r
+#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN\r
+#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN\r
+#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN\r
+#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN\r
+#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN\r
+#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN\r
+#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN\r
+\r
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F19B5C8) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MCO_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_MCOSource_NoClock ((uint8_t)0x00)\r
+#define RCC_MCOSource_SYSCLK ((uint8_t)0x01)\r
+#define RCC_MCOSource_HSI ((uint8_t)0x02)\r
+#define RCC_MCOSource_MSI ((uint8_t)0x03)\r
+#define RCC_MCOSource_HSE ((uint8_t)0x04)\r
+#define RCC_MCOSource_PLLCLK ((uint8_t)0x05)\r
+#define RCC_MCOSource_LSI ((uint8_t)0x06)\r
+#define RCC_MCOSource_LSE ((uint8_t)0x07)\r
+\r
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \\r
+ ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_MSI) || \\r
+ ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK) || \\r
+ ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MCO_Output_Divider \r
+ * @{\r
+ */\r
+\r
+#define RCC_MCODiv_1 ((uint8_t)0x00)\r
+#define RCC_MCODiv_2 ((uint8_t)0x10)\r
+#define RCC_MCODiv_4 ((uint8_t)0x20)\r
+#define RCC_MCODiv_8 ((uint8_t)0x30)\r
+#define RCC_MCODiv_16 ((uint8_t)0x40)\r
+\r
+#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \\r
+ ((DIV) == RCC_MCODiv_4) || ((DIV) == RCC_MCODiv_8) || \\r
+ ((DIV) == RCC_MCODiv_16))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_Flag \r
+ * @{\r
+ */\r
+\r
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)\r
+#define RCC_FLAG_MSIRDY ((uint8_t)0x29)\r
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)\r
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)\r
+#define RCC_FLAG_LSERDY ((uint8_t)0x49)\r
+#define RCC_FLAG_LSIRDY ((uint8_t)0x41)\r
+#define RCC_FLAG_OBLRST ((uint8_t)0x59)\r
+#define RCC_FLAG_PINRST ((uint8_t)0x5A)\r
+#define RCC_FLAG_PORRST ((uint8_t)0x5B)\r
+#define RCC_FLAG_SFTRST ((uint8_t)0x5C)\r
+#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)\r
+#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)\r
+#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)\r
+\r
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+ ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \\r
+ ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \\r
+ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \\r
+ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \\r
+ ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \\r
+ ((FLAG) == RCC_FLAG_WWDGRST))\r
+\r
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the RCC clock configuration to the default reset state */\r
+void RCC_DeInit(void);\r
+\r
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/\r
+void RCC_HSEConfig(uint8_t RCC_HSE);\r
+ErrorStatus RCC_WaitForHSEStartUp(void);\r
+void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);\r
+void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);\r
+void RCC_MSICmd(FunctionalState NewState);\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);\r
+void RCC_HSICmd(FunctionalState NewState);\r
+void RCC_LSEConfig(uint8_t RCC_LSE);\r
+void RCC_LSICmd(FunctionalState NewState);\r
+void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);\r
+void RCC_PLLCmd(FunctionalState NewState);\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);\r
+\r
+/* System, AHB and APB busses clocks configuration functions ******************/\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);\r
+uint8_t RCC_GetSYSCLKSource(void);\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK);\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK);\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
+\r
+/* Peripheral clocks configuration functions **********************************/\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);\r
+void RCC_RTCCLKCmd(FunctionalState NewState);\r
+void RCC_RTCResetCmd(FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);\r
+void RCC_ClearFlag(void);\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_RCC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff