--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_tim.h\r
+ * @author MCD Application Team\r
+ * @version V3.3.0\r
+ * @date 04/16/2010\r
+ * @brief This file contains all the functions prototypes for the TIM firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_TIM_H\r
+#define __STM32F10x_TIM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup TIM_Exported_Types\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief TIM Time Base Init structure definition\r
+ * @note This sturcture is used with all TIMx except for TIM6 and TIM7. \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.\r
+ This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+ uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active\r
+ Auto-Reload Register at the next update event.\r
+ This parameter must be a number between 0x0000 and 0xFFFF. */ \r
+\r
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.\r
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */\r
+\r
+ uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter\r
+ reaches zero, an update event is generated and counting restarts\r
+ from the RCR value (N).\r
+ This means in PWM mode that (N+1) corresponds to:\r
+ - the number of PWM periods in edge-aligned mode\r
+ - the number of half PWM period in center-aligned mode\r
+ This parameter must be a number between 0x00 and 0xFF. \r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+} TIM_TimeBaseInitTypeDef; \r
+\r
+/** \r
+ * @brief TIM Output Compare Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_state */\r
+\r
+ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_state\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+} TIM_OCInitTypeDef;\r
+\r
+/** \r
+ * @brief TIM Input Capture Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.\r
+ This parameter can be a value of @ref TIM_Channel */\r
+\r
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint16_t TIM_ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between 0x0 and 0xF */\r
+} TIM_ICInitTypeDef;\r
+\r
+/** \r
+ * @brief BDTR structure definition \r
+ * @note This sturcture is used only with TIM1 and TIM8. \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.\r
+ This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */\r
+\r
+ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.\r
+ This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */\r
+\r
+ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.\r
+ This parameter can be a value of @ref Lock_level */ \r
+\r
+ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the\r
+ switching-on of the outputs.\r
+ This parameter can be a number between 0x00 and 0xFF */\r
+\r
+ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. \r
+ This parameter can be a value of @ref Break_Input_enable_disable */\r
+\r
+ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.\r
+ This parameter can be a value of @ref Break_Polarity */\r
+\r
+ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. \r
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */\r
+} TIM_BDTRInitTypeDef;\r
+\r
+/** @defgroup TIM_Exported_constants \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10)|| \\r
+ ((PERIPH) == TIM11)|| \\r
+ ((PERIPH) == TIM12)|| \\r
+ ((PERIPH) == TIM13)|| \\r
+ ((PERIPH) == TIM14)|| \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17))\r
+\r
+/* LIST1: TIM 1 and 8 */\r
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM8))\r
+\r
+/* LIST2: TIM 1, 8, 15 16 and 17 */\r
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17)) \r
+\r
+/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */\r
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8)) \r
+ \r
+/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */\r
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17))\r
+\r
+/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ \r
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM15)) \r
+\r
+/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */\r
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM12)|| \\r
+ ((PERIPH) == TIM15))\r
+\r
+/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */\r
+#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM12)|| \\r
+ ((PERIPH) == TIM15)) \r
+\r
+/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ \r
+#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10)|| \\r
+ ((PERIPH) == TIM11)|| \\r
+ ((PERIPH) == TIM12)|| \\r
+ ((PERIPH) == TIM13)|| \\r
+ ((PERIPH) == TIM14)|| \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17))\r
+\r
+/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */\r
+#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17)) \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_and_PWM_modes \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCMode_Timing ((uint16_t)0x0000)\r
+#define TIM_OCMode_Active ((uint16_t)0x0010)\r
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)\r
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)\r
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)\r
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)\r
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2))\r
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2) || \\r
+ ((MODE) == TIM_ForcedAction_Active) || \\r
+ ((MODE) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_One_Pulse_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_OPMode_Single ((uint16_t)0x0008)\r
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)\r
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
+ ((MODE) == TIM_OPMode_Repetitive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Channel \r
+ * @{\r
+ */\r
+\r
+#define TIM_Channel_1 ((uint16_t)0x0000)\r
+#define TIM_Channel_2 ((uint16_t)0x0004)\r
+#define TIM_Channel_3 ((uint16_t)0x0008)\r
+#define TIM_Channel_4 ((uint16_t)0x000C)\r
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3) || \\r
+ ((CHANNEL) == TIM_Channel_4))\r
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2))\r
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Clock_Division_CKD \r
+ * @{\r
+ */\r
+\r
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)\r
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)\r
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)\r
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
+ ((DIV) == TIM_CKD_DIV2) || \\r
+ ((DIV) == TIM_CKD_DIV4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Counter_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_CounterMode_Up ((uint16_t)0x0000)\r
+#define TIM_CounterMode_Down ((uint16_t)0x0010)\r
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)\r
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)\r
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)\r
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \\r
+ ((MODE) == TIM_CounterMode_Down) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPolarity_High ((uint16_t)0x0000)\r
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)\r
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
+ ((POLARITY) == TIM_OCPolarity_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_Polarity \r
+ * @{\r
+ */\r
+ \r
+#define TIM_OCNPolarity_High ((uint16_t)0x0000)\r
+#define TIM_OCNPolarity_Low ((uint16_t)0x0008)\r
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \\r
+ ((POLARITY) == TIM_OCNPolarity_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OutputState_Disable ((uint16_t)0x0000)\r
+#define TIM_OutputState_Enable ((uint16_t)0x0001)\r
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
+ ((STATE) == TIM_OutputState_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_N_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OutputNState_Disable ((uint16_t)0x0000)\r
+#define TIM_OutputNState_Enable ((uint16_t)0x0004)\r
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \\r
+ ((STATE) == TIM_OutputNState_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Capture_Compare_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_CCx_Enable ((uint16_t)0x0001)\r
+#define TIM_CCx_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
+ ((CCX) == TIM_CCx_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Capture_Compare_N_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_CCxN_Enable ((uint16_t)0x0004)\r
+#define TIM_CCxN_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \\r
+ ((CCXN) == TIM_CCxN_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Break_Input_enable_disable \r
+ * @{\r
+ */\r
+\r
+#define TIM_Break_Enable ((uint16_t)0x1000)\r
+#define TIM_Break_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \\r
+ ((STATE) == TIM_Break_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Break_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_BreakPolarity_Low ((uint16_t)0x0000)\r
+#define TIM_BreakPolarity_High ((uint16_t)0x2000)\r
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \\r
+ ((POLARITY) == TIM_BreakPolarity_High))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_AOE_Bit_Set_Reset \r
+ * @{\r
+ */\r
+\r
+#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)\r
+#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \\r
+ ((STATE) == TIM_AutomaticOutput_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Lock_level \r
+ * @{\r
+ */\r
+\r
+#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)\r
+#define TIM_LOCKLevel_1 ((uint16_t)0x0100)\r
+#define TIM_LOCKLevel_2 ((uint16_t)0x0200)\r
+#define TIM_LOCKLevel_3 ((uint16_t)0x0300)\r
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \\r
+ ((LEVEL) == TIM_LOCKLevel_1) || \\r
+ ((LEVEL) == TIM_LOCKLevel_2) || \\r
+ ((LEVEL) == TIM_LOCKLevel_3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OSSIState_Enable ((uint16_t)0x0400)\r
+#define TIM_OSSIState_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \\r
+ ((STATE) == TIM_OSSIState_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OSSRState_Enable ((uint16_t)0x0800)\r
+#define TIM_OSSRState_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \\r
+ ((STATE) == TIM_OSSRState_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Idle_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCIdleState_Set ((uint16_t)0x0100)\r
+#define TIM_OCIdleState_Reset ((uint16_t)0x0000)\r
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \\r
+ ((STATE) == TIM_OCIdleState_Reset))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_N_Idle_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCNIdleState_Set ((uint16_t)0x0200)\r
+#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)\r
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \\r
+ ((STATE) == TIM_OCNIdleState_Reset))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)\r
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)\r
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
+ ((POLARITY) == TIM_ICPolarity_Falling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
+ connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC2, IC1, IC4 or IC3, respectively. */\r
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_TRC))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_interrupt_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_IT_Update ((uint16_t)0x0001)\r
+#define TIM_IT_CC1 ((uint16_t)0x0002)\r
+#define TIM_IT_CC2 ((uint16_t)0x0004)\r
+#define TIM_IT_CC3 ((uint16_t)0x0008)\r
+#define TIM_IT_CC4 ((uint16_t)0x0010)\r
+#define TIM_IT_COM ((uint16_t)0x0020)\r
+#define TIM_IT_Trigger ((uint16_t)0x0040)\r
+#define TIM_IT_Break ((uint16_t)0x0080)\r
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))\r
+\r
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
+ ((IT) == TIM_IT_CC1) || \\r
+ ((IT) == TIM_IT_CC2) || \\r
+ ((IT) == TIM_IT_CC3) || \\r
+ ((IT) == TIM_IT_CC4) || \\r
+ ((IT) == TIM_IT_COM) || \\r
+ ((IT) == TIM_IT_Trigger) || \\r
+ ((IT) == TIM_IT_Break))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Base_address \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)\r
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)\r
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)\r
+#define TIM_DMABase_DIER ((uint16_t)0x0003)\r
+#define TIM_DMABase_SR ((uint16_t)0x0004)\r
+#define TIM_DMABase_EGR ((uint16_t)0x0005)\r
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)\r
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)\r
+#define TIM_DMABase_CCER ((uint16_t)0x0008)\r
+#define TIM_DMABase_CNT ((uint16_t)0x0009)\r
+#define TIM_DMABase_PSC ((uint16_t)0x000A)\r
+#define TIM_DMABase_ARR ((uint16_t)0x000B)\r
+#define TIM_DMABase_RCR ((uint16_t)0x000C)\r
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)\r
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)\r
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)\r
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)\r
+#define TIM_DMABase_BDTR ((uint16_t)0x0011)\r
+#define TIM_DMABase_DCR ((uint16_t)0x0012)\r
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
+ ((BASE) == TIM_DMABase_CR2) || \\r
+ ((BASE) == TIM_DMABase_SMCR) || \\r
+ ((BASE) == TIM_DMABase_DIER) || \\r
+ ((BASE) == TIM_DMABase_SR) || \\r
+ ((BASE) == TIM_DMABase_EGR) || \\r
+ ((BASE) == TIM_DMABase_CCMR1) || \\r
+ ((BASE) == TIM_DMABase_CCMR2) || \\r
+ ((BASE) == TIM_DMABase_CCER) || \\r
+ ((BASE) == TIM_DMABase_CNT) || \\r
+ ((BASE) == TIM_DMABase_PSC) || \\r
+ ((BASE) == TIM_DMABase_ARR) || \\r
+ ((BASE) == TIM_DMABase_RCR) || \\r
+ ((BASE) == TIM_DMABase_CCR1) || \\r
+ ((BASE) == TIM_DMABase_CCR2) || \\r
+ ((BASE) == TIM_DMABase_CCR3) || \\r
+ ((BASE) == TIM_DMABase_CCR4) || \\r
+ ((BASE) == TIM_DMABase_BDTR) || \\r
+ ((BASE) == TIM_DMABase_DCR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Burst_Length \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)\r
+#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)\r
+#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)\r
+#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)\r
+#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)\r
+#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)\r
+#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)\r
+#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)\r
+#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)\r
+#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)\r
+#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)\r
+#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)\r
+#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)\r
+#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)\r
+#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)\r
+#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)\r
+#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)\r
+#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)\r
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \\r
+ ((LENGTH) == TIM_DMABurstLength_2Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_3Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_4Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_5Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_6Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_7Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_8Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_9Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_10Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_11Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_12Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_13Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_14Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_15Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_16Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_17Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_18Bytes))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMA_Update ((uint16_t)0x0100)\r
+#define TIM_DMA_CC1 ((uint16_t)0x0200)\r
+#define TIM_DMA_CC2 ((uint16_t)0x0400)\r
+#define TIM_DMA_CC3 ((uint16_t)0x0800)\r
+#define TIM_DMA_CC4 ((uint16_t)0x1000)\r
+#define TIM_DMA_COM ((uint16_t)0x2000)\r
+#define TIM_DMA_Trigger ((uint16_t)0x4000)\r
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)\r
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)\r
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)\r
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)\r
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Internal_Trigger_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_TS_ITR0 ((uint16_t)0x0000)\r
+#define TIM_TS_ITR1 ((uint16_t)0x0010)\r
+#define TIM_TS_ITR2 ((uint16_t)0x0020)\r
+#define TIM_TS_ITR3 ((uint16_t)0x0030)\r
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)\r
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)\r
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)\r
+#define TIM_TS_ETRF ((uint16_t)0x0070)\r
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3) || \\r
+ ((SELECTION) == TIM_TS_TI1F_ED) || \\r
+ ((SELECTION) == TIM_TS_TI1FP1) || \\r
+ ((SELECTION) == TIM_TS_TI2FP2) || \\r
+ ((SELECTION) == TIM_TS_ETRF))\r
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_TIx_External_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)\r
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)\r
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)\r
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \\r
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \\r
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Polarity \r
+ * @{\r
+ */ \r
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)\r
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)\r
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Prescaler_Reload_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)\r
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)\r
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Forced_Action \r
+ * @{\r
+ */\r
+\r
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)\r
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)\r
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
+ ((ACTION) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Encoder_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)\r
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)\r
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)\r
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
+ ((MODE) == TIM_EncoderMode_TI2) || \\r
+ ((MODE) == TIM_EncoderMode_TI12))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup TIM_Event_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_EventSource_Update ((uint16_t)0x0001)\r
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)\r
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)\r
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)\r
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)\r
+#define TIM_EventSource_COM ((uint16_t)0x0020)\r
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)\r
+#define TIM_EventSource_Break ((uint16_t)0x0080)\r
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Update_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller. */\r
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
+ ((SOURCE) == TIM_UpdateSource_Regular))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Ouput_Compare_Preload_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)\r
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
+ ((STATE) == TIM_OCPreload_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Ouput_Compare_Fast_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCFast_Enable ((uint16_t)0x0004)\r
+#define TIM_OCFast_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
+ ((STATE) == TIM_OCFast_Disable))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Ouput_Compare_Clear_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCClear_Enable ((uint16_t)0x0080)\r
+#define TIM_OCClear_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
+ ((STATE) == TIM_OCClear_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Trigger_Output_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)\r
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)\r
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)\r
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)\r
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)\r
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)\r
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)\r
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)\r
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
+ ((SOURCE) == TIM_TRGOSource_Enable) || \\r
+ ((SOURCE) == TIM_TRGOSource_Update) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)\r
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)\r
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)\r
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)\r
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
+ ((MODE) == TIM_SlaveMode_Gated) || \\r
+ ((MODE) == TIM_SlaveMode_Trigger) || \\r
+ ((MODE) == TIM_SlaveMode_External1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Master_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)\r
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
+ ((STATE) == TIM_MasterSlaveMode_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Flags \r
+ * @{\r
+ */\r
+\r
+#define TIM_FLAG_Update ((uint16_t)0x0001)\r
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)\r
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)\r
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)\r
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)\r
+#define TIM_FLAG_COM ((uint16_t)0x0020)\r
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)\r
+#define TIM_FLAG_Break ((uint16_t)0x0080)\r
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)\r
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)\r
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)\r
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)\r
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
+ ((FLAG) == TIM_FLAG_CC1) || \\r
+ ((FLAG) == TIM_FLAG_CC2) || \\r
+ ((FLAG) == TIM_FLAG_CC3) || \\r
+ ((FLAG) == TIM_FLAG_CC4) || \\r
+ ((FLAG) == TIM_FLAG_COM) || \\r
+ ((FLAG) == TIM_FLAG_Trigger) || \\r
+ ((FLAG) == TIM_FLAG_Break) || \\r
+ ((FLAG) == TIM_FLAG_CC1OF) || \\r
+ ((FLAG) == TIM_FLAG_CC2OF) || \\r
+ ((FLAG) == TIM_FLAG_CC3OF) || \\r
+ ((FLAG) == TIM_FLAG_CC4OF))\r
+ \r
+ \r
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Filer_Value \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Filter \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void TIM_DeInit(TIM_TypeDef* TIMx);\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_TIM_H */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff