--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32l1xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 2-June-2011\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
+ * This file contains the system clock configuration for STM32L1xx Ultra\r
+ * Low Medium-density devices, and is generated by the clock configuration\r
+ * tool "STM32L1xx_Clock_Configuration_V1.0.0.xls".\r
+ * \r
+ * 1. This file provides two functions and one global variable to be called from \r
+ * user application:\r
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier\r
+ * and Divider factors, AHB/APBx prescalers and Flash settings),\r
+ * depending on the configuration made in the clock xls tool. \r
+ * This function is called at startup just after reset and \r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32l1xx_md.s" file.\r
+ * \r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick \r
+ * timer or configure other parameters.\r
+ * \r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution. \r
+ * \r
+ * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.\r
+ * Then SystemInit() function is called, in "startup_stm32l1xx_md.s" file, to\r
+ * configure the system clock before to branch to main program. \r
+ * \r
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()\r
+ * function will do nothing and MSI still used as system clock source. User can \r
+ * add some code to deal with this issue inside the SetSysClock() function. \r
+ * \r
+ * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define\r
+ * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or\r
+ * through PLL, and you are using different crystal you have to adapt the HSE\r
+ * value to your own configuration.\r
+ * \r
+ * 5. This file configures the system clock as follows: \r
+ *=============================================================================\r
+ * System Clock Configuration\r
+ *=============================================================================\r
+ * System clock source | HSI\r
+ *----------------------------------------------------------------------------- \r
+ * SYSCLK | 16000000 Hz\r
+ *----------------------------------------------------------------------------- \r
+ * HCLK | 16000000 Hz\r
+ *----------------------------------------------------------------------------- \r
+ * AHB Prescaler | 1\r
+ *----------------------------------------------------------------------------- \r
+ * APB1 Prescaler | 1\r
+ *----------------------------------------------------------------------------- \r
+ * APB2 Prescaler | 1\r
+ *----------------------------------------------------------------------------- \r
+ * HSE Frequency | 8000000 Hz\r
+ *----------------------------------------------------------------------------- \r
+ * PLL DIV | Not Used\r
+ *----------------------------------------------------------------------------- \r
+ * PLL MUL | Not Used\r
+ *----------------------------------------------------------------------------- \r
+ * VDD | 3.3 V\r
+ *----------------------------------------------------------------------------- \r
+ * Vcore | 1.8 V (Range 1)\r
+ *----------------------------------------------------------------------------- \r
+ * Flash Latency | 0 WS\r
+ *----------------------------------------------------------------------------- \r
+ * Require 48MHz for USB clock | Disabled\r
+ *----------------------------------------------------------------------------- \r
+ *=============================================================================\r
+ ****************************************************************************** \r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32l1xx_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32L1xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32l1xx.h"\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Defines\r
+ * @{\r
+ */\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */ \r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. \r
+ This value must be a multiple of 0x200. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Variables\r
+ * @{\r
+ */\r
+uint32_t SystemCoreClock = 16000000;\r
+__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\r
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static void SetSysClock(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the Embedded Flash Interface, the PLL and update the \r
+ * SystemCoreClock variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit (void)\r
+{\r
+ /*!< Set MSION bit */\r
+ RCC->CR |= (uint32_t)0x00000100;\r
+\r
+ /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
+ RCC->CFGR &= (uint32_t)0x88FFC00C;\r
+ \r
+ /*!< Reset HSION, HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xEEFEFFFE;\r
+\r
+ /*!< Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
+ RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
+\r
+ /*!< Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+ \r
+ /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */\r
+ SetSysClock();\r
+\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */\r
+#else\r
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * \r
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI \r
+ * value as defined by the MSI range.\r
+ * \r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature. \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value\r
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate (void)\r
+{\r
+ uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+ \r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* MSI used as system clock */\r
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\r
+ SystemCoreClock = (32768 * (1 << (msirange + 1)));\r
+ break;\r
+ case 0x04: /* HSI used as system clock */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ case 0x08: /* HSE used as system clock */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+ case 0x0C: /* PLL used as system clock */\r
+ /* Get PLL clock source and multiplication factor ----------------------*/\r
+ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
+ plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
+ pllmul = PLLMulTable[(pllmul >> 18)];\r
+ plldiv = (plldiv >> 22) + 1;\r
+ \r
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
+\r
+ if (pllsource == 0x00)\r
+ {\r
+ /* HSI oscillator clock selected as PLL clock entry */\r
+ SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);\r
+ }\r
+ else\r
+ {\r
+ /* HSE selected as PLL clock entry */\r
+ SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);\r
+ }\r
+ break;\r
+ default: /* MSI used as system clock */\r
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\r
+ SystemCoreClock = (32768 * (1 << (msirange + 1)));\r
+ break;\r
+ }\r
+ /* Compute HCLK clock frequency --------------------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+ /* HCLK clock frequency */\r
+ SystemCoreClock >>= tmp;\r
+}\r
+\r
+/**\r
+ * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash \r
+ * settings.\r
+ * @note This function should be called only once the RCC clock configuration \r
+ * is reset to the default reset state (done in SystemInit() function). \r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClock(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSIStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+ /* Enable HSI */\r
+ RCC->CR |= ((uint32_t)RCC_CR_HSION);\r
+ \r
+ /* Wait till HSI is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSIStatus = RCC->CR & RCC_CR_HSIRDY;\r
+ } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));\r
+\r
+ if ((RCC->CR & RCC_CR_HSIRDY) != RESET)\r
+ {\r
+ HSIStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSIStatus = (uint32_t)0x00;\r
+ }\r
+ \r
+ if (HSIStatus == (uint32_t)0x01)\r
+ {\r
+ /* Flash 0 wait state */\r
+ FLASH->ACR &= ~FLASH_ACR_LATENCY;\r
+ \r
+ /* Disable Prefetch Buffer */\r
+ FLASH->ACR &= ~FLASH_ACR_PRFTEN;\r
+\r
+ /* Disable 64-bit access */\r
+ FLASH->ACR &= ~FLASH_ACR_ACC64;\r
+ \r
+\r
+ /* Power enable */\r
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+ \r
+ /* Select the Voltage Range 1 (1.8 V) */\r
+ PWR->CR = PWR_CR_VOS_0;\r
+ \r
+ \r
+ /* Wait Until the Voltage Regulator is ready */\r
+ while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+ {\r
+ }\r
+ \r
+ /* HCLK = SYSCLK /1*/\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ /* PCLK2 = HCLK /1*/\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK /1*/\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+ \r
+ /* Select HSI as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;\r
+\r
+ /* Wait till HSI is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* If HSI fails to start-up, the application will have wrong clock\r
+ configuration. User can add here some code to deal with this error */\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff