jtag/adapter: add command 'adapter serial'

[fw/openocd] / doc / openocd.texi

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 9ff2e2e5213bd6cb24fdfbfbbe33e7c32fd71c62..286943643798e9a8017a0d9e7476be39ac851dea 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2367,6 +2367,14 @@ The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dm
 This command is only available if your libusb1 is at least version 1.0.16.
 @end deffn
 
+@deffn {Config Command} {adapter serial} serial_string
+Specifies the @var{serial_string} of the adapter to use.
+If this command is not specified, serial strings are not checked.
+No adapter uses this command, so far.
+The following adapters have their own command to specify the serial string:
+cmsis_dap, ft232r, ftdi, hla, jlink, kitprog, presto, st-link, vsllink, xds110.
+@end deffn
+
 @section Interface Drivers
 
 Each of the interface drivers listed here must be explicitly
@@ -2833,7 +2841,7 @@ Reset the current configuration.
 @deffn {Command} {jlink config write}
 Write the current configuration to the internal persistent storage.
 @end deffn
-@deffn {Command} {jlink emucom write <channel> <data>}
+@deffn {Command} {jlink emucom write} <channel> <data>
 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
 pairs.
 
@@ -2843,7 +2851,7 @@ the EMUCOM channel 0x10:
 > jlink emucom write 0x10 aa0b23
 @end example
 @end deffn
-@deffn {Command} {jlink emucom read <channel> <length>}
+@deffn {Command} {jlink emucom read} <channel> <length>
 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
 pairs.
 
@@ -7206,7 +7214,7 @@ as per the following example.
 flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
 @end example
 
-@deffn {Command} {stm32f2x otp } num (@option{enable}|@option{disable}|@option{show})
+@deffn {Command} {stm32f2x otp} num (@option{enable}|@option{disable}|@option{show})
 Enables or disables OTP write commands for bank @var{num}.
 The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
@@ -7643,7 +7651,7 @@ Some tms470-specific commands are defined:
 Saves programming keys in a register, to enable flash erase and write commands.
 @end deffn
 
-@deffn {Command} {tms470 osc_mhz} clock_mhz
+@deffn {Command} {tms470 osc_megahertz} clock_mhz
 Reports the clock speed, which is used to calculate timings.
 @end deffn
 
@@ -8678,7 +8686,7 @@ If the control block location is not known, OpenOCD starts searching for it.
 Stop RTT.
 @end deffn
 
-@deffn {Command} {rtt polling_interval [interval]}
+@deffn {Command} {rtt polling_interval} [interval]
 Display the polling interval.
 If @var{interval} is provided, set the polling interval.
 The polling interval determines (in milliseconds) how often the up-channels are
@@ -9026,7 +9034,7 @@ Enable (@option{on}) or disable (@option{off}) the CTI.
 Displays a register dump of the CTI.
 @end deffn
 
-@deffn {Command} {$cti_name write } @var{reg_name} @var{value}
+@deffn {Command} {$cti_name write} @var{reg_name} @var{value}
 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
 @end deffn
 
@@ -9533,7 +9541,7 @@ cores @emph{except the ARM1176} use the same six bits.
 display information about target caches
 @end deffn
 
-@deffn {Command} {cortex_a dacrfixup [@option{on}|@option{off}]}
+@deffn {Command} {cortex_a dacrfixup} [@option{on}|@option{off}]
 Work around issues with software breakpoints when the program text is
 mapped read-only by the operating system. This option sets the CP15 DACR
 to "all-manager" to bypass MMU permission checks on memory access.
@@ -9571,12 +9579,12 @@ possible (4096) entries are printed.
 @subsection ARMv7-R specific commands
 @cindex Cortex-R
 
-@deffn {Command} {cortex_r dbginit}
+@deffn {Command} {cortex_r4 dbginit}
 Initialize core debug
 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
 @end deffn
 
-@deffn {Command} {cortex_r maskisr} [@option{on}|@option{off}]
+@deffn {Command} {cortex_r4 maskisr} [@option{on}|@option{off}]
 Selects whether interrupts will be processed when single stepping
 @end deffn